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浙江大学学报(工学版)
浙江大学学报(工学版)  2024, Vol. 58 Issue (11): 2290-2298    DOI: 10.3785/j.issn.1008-973X.2024.11.010
计算机技术、控制工程     
低抖动快锁定10.9~12.0 GHz电荷泵锁相环
展永政1(),李仁刚1,李拓1,邹晓峰1,周玉龙1,胡庆生2,3,李连鸣3
1. 山东云海国创云计算装备产业创新中心有限公司，山东 济南 250101
2. 东南大学 射频与光电集成电路研究所，江苏 南京 210096
3. 东南大学 信息科学与工程学院，江苏 南京 210096
Low-jitter fast-locked 10.9−12.0 GHz charge-pump phase-locked loop
Yongzheng ZHAN1(),Rengang LI1,Tuo LI1,Xiaofeng ZOU1,Yulong ZHOU1,Qingsheng HU2,3,Lianming LI3
1. Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Limited Company, Jinan 250101, China
2. Institute of RF- and OE-ICs, Southeast University, Nanjing 210096, China
3. School of Information Science and Engineering, Southeast University, Nanjing 210096, China
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摘要：

基于65 nm CMOS 工艺，设计适用于高速SerDes串行链路的低抖动高速电荷泵锁相环(CPPLL)电路. 通过优化环路带宽以及压控振荡器（VCO）、电荷泵和鉴频鉴相器的电路结构, 抑制电压纹波和内部噪声引起的抖动, 以在满足SerDes链路需要的宽频范围和高速要求的同时, 电荷泵锁相环能够获得较小的抖动偏差和稳定的时钟信号. 包括整个焊盘在内的芯片面积为0.309 mm2. 测试结果表明, 电荷泵锁相环能够实现10.9~12 GHz的输出时钟信号, 其在10 MHz频偏处的相位噪声、参考杂散和品质因数(FoM)分别为?111.47 dBc/Hz、?25.14 dBc和?223.5 dB. 当输入参考频率为706.25 MHz 时, CPPLL能够在600 μs后输出稳定的11.3 GHz时钟信号, 且RMS抖动为973.9 fs, 约为0.065 UI. 在电源电压为1.2 V下, 电路的功耗为47.3 mW. 所设计的锁相环（PLL）电路能够适用于20 Gb/s及以上的高速通信链路系统.
关键词： 压控振荡器(VCO);  电荷泵;  低抖动;  串行链路;  高速    
Abstract:

A low-jitter high-speed charge-pump phase-locked loop (CPPLL) suitable for high-speed SerDes serial link was designed using 65 nm CMOS technology. Loop bandwidth and circuit structure of voltage-controlled oscillator (VCO), charge pump (CP), phase frequency detector (PFD) were optimized to reduce jitter caused by voltage ripple and internal noise. CPPLL can achieve a stable clock signal with the smaller jitter offset while meeting the wide frequency range and high speed requirements of SerDes link. Chip area including the entire pads is 0.309 mm2. The measurement results show that CPPLL can generate a 10.9-12 GHz clock signal and exhibit a phase noise of ?111.47 dBc/Hz and a reference spur of ?25.14 dBc and a figure-of-merit (FoM) of ?223.5 dB at 10 MHz offset. It takes 600 μs to generate a stable 11.3 GHz clock signal, and its RMS jitter is 973.9 fs when the reference frequency is 706.25 MHz, which is approximately 0.065 UI. The power consumption is 47.3 mW at the supply voltage of 1.2 V. The proposed phase-locked loop (PLL) is suitable for high-speed communication link systems at 20 Gb/s and above.
Key words: voltage-controlled oscillator (VCO)    charge pump    low jitter    serial link    high speed
收稿日期: 2023-10-08 出版日期: 2024-10-23
CLC:  TN 432  
基金资助: 山东省自然科学基金资助项目(ZR2022QF146)；山东省自然科学基金创新发展联合基金资助项目(ZR2023LZH004)；中国博士后科学基金资助项目(2024M751268).
作者简介: 展永政 （1989—），男，高级工程师，博士，从事高速集成电路设计的研究. orcid.org 0000-0002-1885-5950. E-mail：sdzyz1989@163.com
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展永政
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周玉龙
胡庆生
李连鸣

引用本文:

展永政,李仁刚,李拓,邹晓峰,周玉龙,胡庆生,李连鸣. 低抖动快锁定10.9~12.0 GHz电荷泵锁相环[J]. 浙江大学学报(工学版), 2024, 58(11): 2290-2298.

Yongzheng ZHAN,Rengang LI,Tuo LI,Xiaofeng ZOU,Yulong ZHOU,Qingsheng HU,Lianming LI. Low-jitter fast-locked 10.9−12.0 GHz charge-pump phase-locked loop. Journal of ZheJiang University (Engineering Science), 2024, 58(11): 2290-2298.

链接本文:

https://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2024.11.010    或    https://www.zjujournals.com/eng/CN/Y2024/V58/I11/2290

图 1  延迟型锁相环的框图
图 2  LC振荡型电荷泵锁相环的框图
图 3  LC振荡型电荷泵锁相环的相位噪声曲线图
图 4  不同环路带宽下的锁定时间变化曲线
图 5  互补交叉耦合负阻LC-VCO的电路图
图 6  交叉耦合管后的VCO输出波形
图 7  不同工艺角下VCO 的压控特性曲线
图 8  VCO 相位噪声
图 9  基于共源共栅的CP电路图
图 10  CP电流匹配的特性曲线
图 11  基于TSPC的PFD电路图
图 12  PFD+CP级联后充电过程
图 13  CP漏电流曲线
图 14  芯片显微照片
图 15  CPPLL的测试平台
图 16  不同工艺角下12.5 GHz CPPLL 频率锁定曲线
图 17  SS工艺角下的CPPLL抖动性能
图 18  锁相环芯片的瞬态测试曲线
图 19  锁相环芯片的相位噪声测试曲线(@11.2 GHz)
图 20  锁相环芯片的参考杂散测试曲线(@11.3 GHz)
文献VCO锁频范围/GHzRMS /ps相位噪声/(dB·Hz?1)参考杂散/dB功耗/mW面积/mm2FoM/dB
本文LC10.9~12.00.9739?111.47@10 MHz?25.1447.30.309?223.5
文献[24]LC1.25~3.1252.17——43.6—?216.8
文献[25]LC6.3~8.71.2?116.6@1 MHz<?50500.72?161.4
文献[26]LC3.60.043?141.1@1 MHz?80.347.270.497?258.7
文献[27]Ring3.27.5?107.9@10 MHz?45.52.730.047?218.1
文献[28]Ring1.25~3.1251.65—?47.6328.80.384?221.1
文献[29]Ring1.2~2.50.25?124.8@1 MHz?468.50.0066?242.7
表 1  65 nm 工艺下的CPPLL性能总结与比较
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