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浙江大学学报(工学版)
JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE)
    
Embedded Flash data fetching acceleration techniques and implementation
WANG Yu-bo1, HUANG Kai1, CHEN Chen1, FENG Jiong2, GE Hai-tong2, YAN Xiao-lang1
1. Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China; 2. Hangzhou C-SKY Micro-system Company, Hangzhou 310027, China
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Abstract  

Some embedded Flash data fetching acceleration techniques based on cache were proposed and implemented, which are used for low-cost, low-power consumption application, including low frequency fast access, backfill hidden with modified critical-word-first strategy, cache-lock with adaptive prefetching, and pre-lookup. With the combination of these techniques, the Flash data fetching performance is improved and the power dissipation is kept low. Simulations show that when the resource on chip (cache size) is limited and the system frequency is low (for some low-power consumption applications), the embedded Flash accelerator with these techniques has higher performance(20%-40% higher) and lower dynamic power consumption (about 40% lower) compared with conventional two-way set-associative cache.

Published: 01 September 2014
CLC:  TN 47  
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Cite this article:

WANG Yu-bo, HUANG Kai, CHEN Chen, FENG Jiong, GE Hai-tong, YAN Xiao-lang. Embedded Flash data fetching acceleration techniques and implementation. JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), 2014, 48(9): 1570-1579.

URL:

http://www.zjujournals.com/eng/10.3785/j.issn.1008-973X.2014.09.005     OR     http://www.zjujournals.com/eng/Y2014/V48/I9/1570


嵌入式Flash读取加速技术及实现

为了解决低成本和低功耗应用中的嵌入式Flash读取速度问题，提出多种基于缓存结构的嵌入式Flash读取加速技术及实现，包括低频快速访问技术、回填隐藏技术和改进型关键字优先预取策略，以及具有自适应预取功能的缓存锁定技术、预查找技术等，通过这些技术的整合应用，在提高Flash读取性能的同时，保持较低的功耗.仿真实验证明：在占用资源（缓存容量）较少，频率较低（用于部分低功耗应用）的环境下，这些技术的应用使加速控制器的加速性能与传统的2路组相联缓存相比得到了明显的提升（20%~40%），同时加速控制器中读加速单元的动态功耗与传统2路组相联缓存相比降低了40%左右.

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