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浙江大学学报(工学版)
J4  2013, Vol. 47 Issue (7): 1213-1217    DOI: 10.3785/j.issn.1008-973X.2013.07.012
    
Low power instruction cache based on adjacent line linking access
XIANG Xiao-yan, CHEN Zhi-jian, MENG Jian-yi, YAN Xiao-lang
Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China
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Abstract  

 The behavior of cache accessing was analyzed. A new low power instruction cache accessing method that links the current cache line and its adjacent cache lines was proposed. When a direct jump between cache lines occurs, the adjacent cache line links are reused to get the accurate way information of the target line. Then the accesses of tag array are reduced and tag lookups are avoided to reduce the dynamic power consumption. When a cache line is evicted, only its adjacent cache line links should be checked and invalidated to keep the correctness of the links. Experiment results show that dynamic power consumption can be reduced by 6% on average with the new method compared to the traditional way memorization instruction cache．

Published: 01 July 2013
CLC:  TN 332  
  TN 47  
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Cite this article:

XIANG Xiao-yan, CHEN Zhi-jian, MENG Jian-yi, YAN Xiao-lang. Low power instruction cache based on adjacent line linking access. J4, 2013, 47(7): 1213-1217.

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http://www.zjujournals.com/eng/10.3785/j.issn.1008-973X.2013.07.012     OR     http://www.zjujournals.com/eng/Y2013/V47/I7/1213


基于邻行链接访问的低功耗指令高速缓存

通过分析高速缓存访问的局部性原理,提出当前高速缓存访问行与若干紧邻行链接访问的低功耗指令缓存访问方法.该方法能够在发生相对跳转时依托于相邻行之间的访问链接信息,精确获得跳转目标行的路访问信息,减少对高速缓存标志存储器的访问,达到降低动态功耗的目的.在高速缓存行发生替换时,仅需检测并清除被替换行相邻范围内的若干缓存行的链接信息,从而实现链接关系的正确性.与基于路记忆访问的高速缓存器相比,应用该方法的高速缓存器的动态功耗可以平均减少6%.

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