A hardware optimizing implementation with compressing attends was proposed for the problem that the critical path of traditional Gaussian filter hardware implementation is long and the logic delay is large. In the Gaussian filter hardware optimizing implementation process, shift operation was used to achieve multiplication and division calculation in order to avoid the use of multipliers and dividers. Three kinds of circuit structure, i.e. Carry Save Adder (CSA), 4-2 compressor based on two multiplexer (MUX), and tree structure for compressing attends, were used to compress the nine attends at three levels. After optimizing, only one full adder was needed to obtain the sum of results. The experimental results show that the hardware optimizing implementation of Gaussian filter with compressing attends can shorten the critial path and reduce the logic delay. The proposed method reduces the logic delay by32.48% and occupies less Macro Statistics of Adders compared with the traditional implementation. The saved Macro Statistics of Adders can provide greater design freedom for the following image processing units．
CHEN Chao, LUO Xiao-hua, CHEN Shu-qun, YU Guo-jun. Optimizing implementation of Gaussian filter based on field programmable gate array. JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), 2017, 51(5): 969-975.
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