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| Cache modeling for MPSoC performance estimation |
| XIU Si-wen1, LI Yan-zhe1, HUANG Kai1, MA De2, YAN Rong-jie3, YAN Xiao-lang1 |
1. Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China; 2. Microelectronics CAD Center, Hangzhou Dianzi University, Hangzhou 310018, China;
3. Institute of Software, Chinese Academy of Sciences, Beijing 100080, China |
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Abstract The disadvantages of existing cache modeling techniques for MPSoC performance estimation were analyzed. An static analysis and dynamic annotation combined cache modeling technique for native simulation was proposed. The technique employs GCC profiling, avoids tag-search for hit/miss judgment, and coarsens the granularity of cache updating. An accurate address mapping table for instruction and all types of data variables was established, which improves both simulation speed and estimation accuracy. Multi-level cache modeling was considered, which extends support for multi-processor platform. Experimental results show that the proposed technique can significantly reduce the simulation time and improve the accuracy of estimation result compared with existing techniques．
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Published: 10 September 2015
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面向MPSoC性能评估的高速缓存建模技术
分析现有的面向MPSoC性能评估的高速缓存建模技术的缺点,提出用于本机模拟的静态分析和动态标注相结合的缓存建模技术.该技术采用GCC剖析,避免了命中判断时标签比较,扩展了缓存更新的粒度.建立准确的指令和各类型变量在目标平台的地址映射表,提高了仿真速度和评估的准确性.该技术支持对多级缓存的建模,扩展了对多处理器平台的支持.实验结果表明,该技术的评估速度和准确性均优于现有技术．
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