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| Power-efficient image blending engine design based on self-adaptive pipeline |
| TAN Teng-fei1, MA De1, HUANG Kai2, MA Qi1 |
| 1. Microelectronic CAD Center, Hangzhou Dianzi University, Hangzhou 310018, China; 2. Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China |
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Abstract A power efficient self-adaptive pipeline and corresponding on-chip buffer architecture was proposed according to the characteristics of multi-image blending. The architecture supports four-image inputted with both RGB and YCbCr color format based on ITU-R BT.601 and ITU-R BT.709 standard. Depending on color format of each input image, the proposed blending engine automatically adapted pipeline architecture and work status of each stage to improve power efficiency. Bi-controllable circular buffer structure was adopted to decrease pipeline stalls, keeping pipeline smooth. Selective-fetching pixel and self-adaptive color space conversion techniques were adopted to reduce the power consumption. Experimental results show that the proposed work can achieve better tradeoff of power, area and performance compared with the related works. At the hardware cost of 136000 gate with SMIC90 technology, three-channel blending can be realized for 1080@30fp images in real time with 150 MHz frequency and the lowest power dynamic consumption can achieve 0.065 mW．
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Published: 06 June 2018
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多层图像叠加处理的低功耗自适应流水线设计
针对多层图像叠加处理技术的特点,提出低功耗自适应流水线及片上缓存架构,支持ITU-R BT.601和ITU-R BT.709标准下RGB和YCbCr格式的4层图像叠加显示.该架构根据各层图像格式,自适应调整流水线及各级逻辑工作状态以提高能效比.采用双向可控环形缓存,减少由于缓存状态导致的流水线停顿,保证流水线顺畅工作.采用像素选择性读取、色度空间转换(CSC)自适应等技术进一步降低功耗.实验结果表明：与其他相关设计相比,提出的流水线架构能够取得较好的处理效率和资源消耗比,在SMIC90工艺下硬件资源代价为136000门,工作频率达到150 MHz,能够满足3路1080p@30帧/s图像的实时叠加处理,最低动态功耗达到0.065 mW.
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