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JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE)
    
Functional coverage convergence technique based on genetic algorithm
GAO Shi-yi1, LUO Xiao-hua1, LU Yu-feng1, LIU Fu-chun2, ZHANG Chen-qiu1
1.College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China; 2. College of Engineering, Peking University, Hangzhou 311121, China
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Abstract  

With the development of large-scale integrated circuit, verification plays an increasingly important role in IC design. The functional coverage becomes a standard of IC verification. The key to improve the efficiency of verification has been a hotspot in recent years. A new functional coverage convergence technique based on genetic algorithm was proposed to improve the efficiency of verification in this article. Proportional selection operator, uniform crossover operator, and binary mutation operator were used to get the excellent verification vectors. Those genetic operators were obtained by calculating the probability distribution. An image processing chip named Turbo was selected as the verification model, and the genetic algorithm was embedded in the hierarchical testing platform built in System Verilog. Comparing with the whole random test, the proposed method reduces the generating probability of identical vectors and shortens the simulation time by 25%. In addition, the genetic algorithm improves the verification efficiency.



Published: 01 August 2015
CLC:  TN 47  
Cite this article:

GAO Shi-yi, LUO Xiao-hua, LU Yu-feng, LIU Fu-chun, ZHANG Chen-qiu. Functional coverage convergence technique based on genetic algorithm. JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), 2015, 49(8): 1509-1515.

URL:

http://www.zjujournals.com/eng/10.3785/j.issn.1008-973X.2015.08.015     OR     http://www.zjujournals.com/eng/Y2015/V49/I8/1509


基于遗传算法的功能覆盖率收敛技术

针对集成电路验证向量生成与功能覆盖率收敛的问题,提出一种基于遗传算法的功能覆盖率收敛技术.通过计算分析遗传算法中遗传算子的概率分布函数,获得由比例选择算子、均匀交叉算子以及二元变异算子组成的遗传算法,得到覆盖率广、重复性低的验证向量,在最短仿真时间内达到预先设定的功能覆盖率.实验采用基于Turbo芯片的图像处理硬件加速器作为验证模型,将遗传算法嵌入到以System Verilog语言为基础的层次化验证平台中.结果表明,与全随机向量验证相比,该算法有效增加了功能覆盖率并使仿真时间缩短了25%左右,实现功能覆盖率的快速收敛,提高了验证效率.

[1] PIRKER-FRUHAUF A,KUNZE M. Anovelmethodology to combine and speed-up theverificationprocess ofsimulation and measurement of integrated circuits [C]∥IEEE Autotestcon. Salt Lake City, UT. \[s.n.\]2008: 811.
[2] PIRKER-FRUHAUF A, GALLENT W, KUNZE M, et al.Accelerating of IC verification processusing advancedflexible modularmeasurementsystems and software architectures [C]∥IEEE InternationalInstrumentation and Measurement Technology Conference.Victoria. VancouverIsland. Canada: \[s.n.\] 2008: 18451847.
[3] SPEAR C. SystemVerilog测试平台编写指南[M]. 北京:科学出版社,2009: 6-10.
[4] BERGERON J. Writing testbenches functional verification of HDL models[M]. Dordrecht, Holland: Kluwer Academic Publisher, 2002: 2032.
[5] 赵全利,秦春斌.EDA技术及应用教程[M].北京:机械工业出版社,2009: 1020.
[6] 黄思远,邵智勇,于承兴,等. VMM中功能覆盖率收敛技术[J]现代电子技术, 2010,16(4):1631.
HUANG Si-yuan, SHAO Zhi-yong, YU Cheng-xing, et al. Convergence technology of functional coverage in VMM [J].Modern Electronic Technology,2010,16(4): 1631.
[7] NAWAZ M S, LALI M I, PASHA M A. Formal verification of crossover operator in genetic algorithms using prototype verification system [J].IEEE 9th International Conference onEmerging Technologies (ICET),2013,1109(10):16.
[8] WANG Jia-wen,LIU Zhi-gui, WANG Su-liang,et al. Coverage-directed stimulus generation using a genetic algorithm [J].InternationalSoC Design Conference (ISOCC), 2013,1109(10): 298301.
[9] CORNO F, SANCHEZ E, REORDA MS, et al. Automatic test program generation: a case study [J].IEEE Design & Testof Computers, 2004, 21(2): 102109.
[10] SAMARAH A,HABIBI A, TAHAR S, et al. Automated coverage directed test generation using a cell-based genetic algorithm [C]∥ IEEE International HighLevelDesign Validation and TestWorkshop.Piscataway,NJ: IEEE,2006: 1926.
[11] 罗春,杨军,凌明. 基于遗传算法和覆盖率驱动的功能验证向量自动生成算法[J]. 应用科学学报,2005,23(4): 375379.
LUO Chun, YANG Jun, LING Ming. Coverage of directed vector generation for functional verification using genetic algorithm [J].Journal of AppliedSciences,2005,23(4): 375379.
[12] 苏琳琳,张晓林. 利用自适应遗传算法的芯片功能验证自动测试[J]. 应用科学学报,2011,29(6): 631636.
SU Lin-lin, ZHANG Xiao-lin. Functional coverage verificationusing adaptive genetic algorithm [J].Journal of Applied Sciences,2011,29(6): 631636.
[13] 朱凤龙,邓辉文,李飞,等. 改进交叉算子和变异算子抑制GA算法早熟[J].科学技术与工程,2010,10(6):15401542.
ZHU Feng-long, DEN Hui-wen, LI Fei, et al. A genetic algorithm consists of improved crossover and mutation operators which can inhibit premature [J]. Science Technology and Engineering,2010,10(6): 15401542.

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