通信工程、自动化技术 |
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面向MPSoC性能评估的高速缓存建模技术 |
修思文1, 李彦哲1, 黄凯1, 马德2, 晏荣杰3, 严晓浪1 |
1. 浙江大学 超大规模集成电路研究所,浙江 杭州 310027;2. 杭州电子科技大学 微电子CAD所,浙江 杭州 310018;3. 中国科学院软件研究所,北京 100080 |
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Cache modeling for MPSoC performance estimation |
XIU Si-wen1, LI Yan-zhe1, HUANG Kai1, MA De2, YAN Rong-jie3, YAN Xiao-lang1 |
1. Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China; 2. Microelectronics CAD Center, Hangzhou Dianzi University, Hangzhou 310018, China;
3. Institute of Software, Chinese Academy of Sciences, Beijing 100080, China |
引用本文:
修思文, 李彦哲, 黄凯, 马德, 晏荣杰, 严晓浪. 面向MPSoC性能评估的高速缓存建模技术[J]. 浙江大学学报(工学版), 10.3785/j.issn.1008-973X.2015.07.023.
XIU Si-wen, LI Yan-zhe, HUANG Kai, MA De, YAN Rong-jie, YAN Xiao-lang. Cache modeling for MPSoC performance estimation. JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), 10.3785/j.issn.1008-973X.2015.07.023.
链接本文:
http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2015.07.023
或
http://www.zjujournals.com/eng/CN/Y2015/V49/I7/1367
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