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浙江大学学报(工学版)
通信工程、自动化技术     
面向MPSoC性能评估的高速缓存建模技术
修思文1, 李彦哲1, 黄凯1, 马德2, 晏荣杰3, 严晓浪1
1. 浙江大学 超大规模集成电路研究所,浙江 杭州 310027;2. 杭州电子科技大学 微电子CAD所,浙江 杭州 310018;3. 中国科学院软件研究所,北京 100080
Cache modeling for MPSoC performance estimation
XIU Si-wen1, LI Yan-zhe1, HUANG Kai1, MA De2, YAN Rong-jie3, YAN Xiao-lang1
1. Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China; 2. Microelectronics CAD Center, Hangzhou Dianzi University, Hangzhou 310018, China;
3. Institute of Software, Chinese Academy of Sciences, Beijing 100080, China
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摘要:

分析现有的面向MPSoC性能评估的高速缓存建模技术的缺点,提出用于本机模拟的静态分析和动态标注相结合的缓存建模技术.该技术采用GCC剖析,避免了命中判断时标签比较,扩展了缓存更新的粒度.建立准确的指令和各类型变量在目标平台的地址映射表,提高了仿真速度和评估的准确性.该技术支持对多级缓存的建模,扩展了对多处理器平台的支持.实验结果表明,该技术的评估速度和准确性均优于现有技术.

Abstract:

The disadvantages of existing cache modeling techniques for MPSoC performance estimation were analyzed. An static analysis and dynamic annotation combined cache modeling technique for native simulation was proposed. The technique employs GCC profiling, avoids tag-search for hit/miss judgment, and coarsens the granularity of cache updating. An accurate address mapping table for instruction and all types of data variables was established, which improves both simulation speed and estimation accuracy. Multi-level cache modeling was considered, which extends support for multi-processor platform. Experimental results show that the proposed technique can significantly reduce the simulation time and improve the accuracy of estimation result compared with existing techniques.

出版日期: 2015-09-10
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基金资助:

中央高校基本科研业务费专项资金资助项目(2013QNA5008);国家科技重大专项基金资助项目(2009ZX01030-001-002); 国家自然科学基金资助项目(61100074)

通讯作者: 黄凯,男,副教授     E-mail: huangk@vlsi.zju.edu.cn
作者简介: 修思文(1985—),男,博士生,从事多核处理器设计的研究.E-mail:xiusw@vlsi.zju.edu.cn
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引用本文:

修思文, 李彦哲, 黄凯, 马德, 晏荣杰, 严晓浪. 面向MPSoC性能评估的高速缓存建模技术[J]. 浙江大学学报(工学版), 10.3785/j.issn.1008-973X.2015.07.023.

XIU Si-wen, LI Yan-zhe, HUANG Kai, MA De, YAN Rong-jie, YAN Xiao-lang. Cache modeling for MPSoC performance estimation. JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), 10.3785/j.issn.1008-973X.2015.07.023.

链接本文:

http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2015.07.023        http://www.zjujournals.com/eng/CN/Y2015/V49/I7/1367

[1] JERRAYA A, WOLF W. Multiprocessor systems-on-chips [M]. Amsterdam: Elsevier, 2004.
[2] Martin G. Overview of the MPSoC design challenge [C] ∥ Design Automation Conference. San Francisco: ACM/IEEE, 2006: 274-279.
[3] POSADAS H, HERRERA F, SNCHEZ P, et al. System-level performance analysis in SystemC [C] ∥ Design, Automation and Test in Europe Conference and Exhibition. Paris: IEEE, 2004: 378-383.
[4] KIRNER R, SCHOEBERL M. Modeling the function cache for worst-case execution time analysis [C] ∥ Design Automation Conference. San Diego: ACM/IEEE, 2007: 471-476.
[5] SONG F, MOORE S, DONGARRA J. L2 cache modeling for scientific applications on chip multi-processors [C] ∥ International Conference on Parallel Processing. Xi’an: IEEE, 2007: 51.
[6] LI Y T S, MALIK S, WOLFE A. Cache modeling for real-time software: beyond direct mapped instruction caches [C] ∥ Real-Time Systems Symposium. Los Alamitos: IEEE, 1996: 254-263.
[7] BENINI L, BERTOZZI D, BOGLIOLO A, et al. Mparm: exploring the multi-processor soc design space with system [J]. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 2005, 41(2): 169-182.
[8] EDLER J, HILL M D. Dinero IV trace-driven uniprocessor cache simulator [EB/OL]. [2014-05-23]. http:∥pages.cs.wisc.edu/~markhill/DineroIV.
[9] BINKERT N, BECKMANN B, BLACK G, et al. The gem5 simulator [J]. ACM SIGARCH Computer Architecture News, 2011, 39(2): 17.
[10] POSADAS H, DAZ L, VILLAR E. Fast data-cache modeling for native co-simulation [C] ∥ ASP-DAC. Yokohama: IEEE, 2011: 425-430.
[11] CASTILLO J, POSADAS H, VILLAR E, et al. Fast instruction cache modeling for approximate timed HW/SW co-simulation [C] ∥ Proceedings of the 20th Symposium on Great Lakes Symposium on VLSI. New York: ACM, 2010: 191-196.
[12] WANG Z, HENKEL J. Fast and accurate cache modeling in source-level simulation of embedded software [C] ∥ Proceedings of the Conference on Design, Automation and Test in Europe. Grenoble: IEEE, 2013: 587-592.
[13] SCHNERR J, BRINGMANN O, VIEHL A, et al. High-performance timing simulation of embedded software [C] ∥ Design Automation Conference. Anaheim: IEEE, 2008: 290-295.
[14] KIRCHSTEIGER C M, SCHWEITZER H, TRUMMER C, et al. A software performance simulation methodology for rapid system architecture exploration [C] ∥ 15th IEEE International Conference on Electronics, Circuits and Systems. Juliens: IEEE, 2008: 494-497.
[15] GERIN P, HAMAYUN M M, PTROT F. Native MPSoC co-simulation environment for software performance estimation [C] ∥ Proceedings of the 7th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis. New York: ACM, 2009: 403-412.
[16] YAN R, MA D, HUANG K, et al. Annotation and analysis combined cache modeling for native simulation [C] ∥ Design Automation Conference (ASP-DAC). Singapore: IEEE, 2014: 406-411.
[17] MA D, YAN R, HUANG K, et al. Performance estimation techniques with MPSoC transaction-accurate models [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013, 32(12): 1920-1933.
[18] GNU. Gcov-a test coverage program [EB/OL].[2014-05-23].http:∥gcc.gnu.org/onlinedocs/gcc/Gcov.html.
[19] ARM LTD. ARM920T technical reference manual [EB/OL]. [2014-05-23]. http:∥infocenter.arm.com/help/topic/com.arm.doc.ddi0151c/ARM920T_TRM1_S.pdf.
[20] Embedded Microprocessor Benchmark Consortium. MultiBenchTM 10 Benchmark software [EB/OL]. [2014-05-23]. http:∥www.eembc.org/benchmark/multi_sl.php.
[21] C-SKY MICROSYSTEMS CO., LTD. CK810 introduction [EB/OL]. [2014-05-23]. http:∥www.c-sky.com/product.php?typeid=103.

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