A CNN accelerator design based on a variable-precision systolic-array architecture was proposed to address inefficient resource provisioning and accuracy degradation in existing approaches. At the algorithm level, an entropy-based quantization strategy was introduced to evaluate the information content of each layer, and mixed-precision configurations (INT4/INT8) were assigned across the network. A KL-divergence loss term was incorporated into quantization-aware training to reduce the accuracy degradation caused by low-bit quantization. At the hardware-architecture level, a dedicated field-programmable gate array (FPGA) accelerator was developed to implement the proposed quantization scheme. An output-stationary systolic array was adopted as the computation core, and variable-precision processing elements were integrated into the accelerator. Each processing element was designed with a single digital signal processor (DSP) block and was configured to perform two parallel multiplications to improve computational density. Furthermore, a FIFO-based sliding-window buffer was employed to enhance on-chip data reuse. Batch normalization was fused with convolution to establish an efficient end-to-end processing pipeline. The performance of the proposed accelerator was evaluated on a Xilinx Kintex-7 platform. Results showed that the accelerator achieved a throughput of 96 GOP/s, a latency of 0.56 ms per-image, and a power consumption of 13.54 W, respectively. The proposed design demonstrates implementation feasibility for edge-deployment scenarios.