| Computer Technology, Electronic Communications Technologies |
|
|
|
|
| Error cancellation flip-flop design with lightweight in-situ error correction |
| HAO Zi-yi, XIANG Xiao-yan, CHEN Chen, MENG Jian-yi |
1. College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China;
2. College of Microelectronics, Fudan University, Shanghai, 201203, China |
|
|
|
Abstract A lightweight error cancellation flip-flop based on in-situ error correction was proposed to address the problems of cost and performance in timing error detection and correction techniques. Error cancellation flip-flop could detect timing error by observing the build-in virtual rails, thus no additional cost was introduced in error detection. Based on the observed information of input potential, timing error was directly corrected inside the flip-flop and only 4 additional transistors were utilized to accomplish in-situ error correction. Complicated transition detector for error detection and additional storage cell for error correction were not used in error cancellation flip-flop, so the area and power overhead were ultra-low. To evaluate the timing error tolerance ability and the improving capacity of energy efficiency, the flip-flop was applied into a commercial processor CK802 at SMIC 40 nm technology. Experiment results show that error correction flip-flop can largely decrease area overhead and performance loss of timing error tolerance processor. Compared to the existent technique of art error detection and correction, error correction flip-flop increases the performance of processor by 10.9% at fixed supply voltage and decreases the power consumption by 17.7% under fixed throughput.
|
|
Published: 01 March 2017
|
|
|
|
Cite this article:
HAO Zi-yi, XIANG Xiao-yan, CHEN Chen, MENG Jian-yi. Error cancellation flip-flop design with lightweight in-situ error correction. JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), 2017, 51(3): 605-611.
|
轻量级现场纠正的错误消除寄存器设计
针对时序错误实时检测和纠正技术中存在的检错成本和纠错性能问题,提出一种基于轻量级现场纠错技术的错误消除寄存器.错误消除寄存器采用自带的内部虚拟节点作为错误检测点,以无额外成本的方式实现时序错误的实时检测；基于观测到的高低电平信息,直接在寄存器内部进行错误纠正,通过仅增加4个额外晶体管的代价,完成即时的现场纠错.错误消除寄存器没有使用复杂的外置翻转探测电路进行错误检测,并且也没有使用额外的存储单元用于错误纠正,因此引入的额外面积和额外功耗极低.为评估错误消除寄存器的时序容错能力和电路效率提升能力,在中芯国际40 nm工艺下将该寄存器集成到商用嵌入式处理器CK802中进行实验.实验结果表明,错误消除寄存器大幅度降低了容错处理器的面积成本和性能损失,相比现有技术,在同电压下有10.9%的性能提升,在同性能下有17.7%的功耗优化.
|
|
| ［1］ 冯亚勇. 抗PVT变化的自适应电源电压调整电路设计［D］. 哈尔滨: 哈尔滨工业大学, 2011: 13.
FENG Ya-yong. Design of adaptive power supply regulating circuit against PVT fluctuation ［D］. Harbin: Harbin Institute of Technology, 2011: 13.
［2］ 秋攀,乔树山,凌康,等.基于关键路径延时检测的自适应电压缩减技术［J］. 半导体技术, 2015, 40(4): 250-254.
QIU Pan, QIAO Shu-shan, LING Kang, et al. Adaptive voltage scaling technique based on critical path delay monitoring ［J］. Semiconductor Technology,2015, 40(4): 250-254.
［3］ DAS S, ROBERTS D, LEE S, et al. A self-tuning DVS processor using delay-error detection and correction ［J］. IEEE Journal of Solid-State Circuits, 2006, 41(4):792-804.
［4］ TSCHANZ J, BOWMAN K, WALSTRA S, et al. Tunable replica circuits and adaptive voltage-frequency techniques for dynamic voltage, temperature, and aging variation tolerance ［C］ ∥ 2009 Symposium on VLSI Circuits. Kyoto: IEEE, 2009: 112-113.
［5］ 雷庭. 处理器自查错纠错技术：延时故障建模、设计决策与规划［D］.北京：清华大学,2011: 12.
LEI Ting. Error-detection and error-correction technologies for processors: delay fault modeling, design decisions and planning ［D］. Beijing: Tsinghua University, 2011: 12.
［6］ ERNST D, DAS S, LEE S, et al. Razor: circuit-level correction of timing errors for low-power operation ［J］. IEEE Micro, 2004, 24(6): 10-20.
［7］ BOWMAN K, TSCHANZ J, DE V, et al. Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance ［J］. IEEE Journal of Solid-State Circuits,2009, 44(1): 49-63.
［8］ BOWMAN K, TSCHANZ J, LU S, et al. A 45 nmresilient microprocessor core for dynamic variation tolerance ［J］. IEEE Journal of Solid-State Circuits, 2011,46(1): 194-208.
［9］ 邱吉冰,鄢贵海,韩银和,等. 适应宽温环境的集成电路低功耗实现技术［J］. 计算机工程与设计,2016, 37(1): 269-274.
QIU Ji-bing, Yan Gui-hai, Han Yin-he, et al. Low power design technique for IC with wide temperature range ［J］. Computer Engineering and Design,2016,37(1): 269-274.
［10］ KWON I, KIM S, SYLVESTER D, et al. Razor-Lite: a light-weight register for error detection by observing virtual supply rails ［J］. IEEE Journal of Solid-State Circuits, 2014, 49(9): 2054-2066.
［11］ CHAE K, MUKHOPADHYAY S. A dynamic timing error prevention technique in pipelines with time borrowing and clock stretching ［J］. IEEE Transactions on Circuits and Systems I: Regular Papers, 2014, 61(1): 74-83.
［12］ CHOUDHURY M, CHANDRA V, MOHANRAM K,et al. Time-borrowing circuit designs and hardware prototyping for timing error resilience ［J］. IEEE Transactions on Computers, 2014, 63(2): 497-509.
［13］ FOJTIK M, FICK D, SYLVESTER D, et al. Bubble razor: eliminating timing margins in an ARM cortex-M3 processor in 45 nm CMOS using architecturally independent error detection and correction ［J］. IEEE Journal of Solid-State Circuits, 2013, 48(1): 66-81.
［14］ C-SKY Microsystems. 32-bit high performance and low power embedded processor ［EB/OL］. ［2016-03-13］. http:∥www.c-sky.com/down.php？id=39.
［15］ CHOUDHURY M, MOHANRAM K. Masking timing errors on speedpaths in logic circuits ［C］ ∥ In Design, Automation Test in Europe Conference Exhibition. Nice: IEEE, 2009: 87-92.
［16］ DAS S, TOKUNAGA C, BLAAUW D, et al. RazorII: In situ error detection and correction for pvt and ser tolerance ［J］. IEEE Journal of SolidState Circuits, 2009, 44(1): 32-48.
［17］ BULL D, DAS S, BLAAUW D, et al. A power-efficient 32 bit arm processor using timing-error detection and correction for transient-error tolerance and adaptation to pvt variation ［J］. IEEE Journal of Solid-State Circuits, 2011, 46(1): 18-31. |
|
Viewed |
|
|
|
Full text
|
|
|
|
|
Abstract
|
|
|
|
|
Cited |
|
|
|
|
| |
Shared |
|
|
|
|
| |
Discussed |
|
|
|
|
