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New method for low power sequential circuit design
based on clock gating |
| XU Yang, SHEN Ji-zhong |
| Institute of Electronic Circuit and Information System,Zhejiang University,Hangzhou 310027,China |
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Abstract A new method based on clock gating technique was proposed to achieve a more optimal low power design for sequential circuit. First of all, obtain the circuits behavior Karnaugh maps from the next states table or the state-transition diagram. Gate the redundant clock properly according to the actual situation, and gain the redundancy restraining signal. Some redundant clock neednt be blocked if the gating cost is too high. After that, change the marked maintain condition into dontcare condition, draw the next Karnaugh maps of flip-flops, and obtain the excitation functions. Finally, draw the circuit diagram based on the redundancy restraining signal and excitation functions, and make sure that the circuit can self-start. 8421 binary coded decimal (BCD) synchronous decimal up counter and three bit Johnson counter as practical design examples using this new method were studied and simulated by Hspice. Simulation shows that these designs have correct logic function and can achieve large energy saving. Compared to existing designs, the proposed designs have either lower power dissipation or improved performance．
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Published: 01 September 2010
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基于门控时钟的低功耗时序电路设计新方法
为了实现更优化的时序电路低功耗设计,提出一种新的基于门控时钟技术的低功耗时序电路设计方法,设计步骤为：由状态转换表或状态转换图作出各触发器的行为转换表及行为卡诺图；根据实际情况对电路中的冗余时钟进行封锁,综合考虑门控时钟方案在系统功耗上的收益和代价,当门控代价过高时,对冗余的时钟实行部分封锁,得到各触发器的冗余抑制信号；将前一步骤中的保持项改为无关项,作出各触发器的次态卡诺图,得到激励函数；由冗余抑制信号和激励函数画出电路图,并检验电路能否自启动.以8421二-十进制代码同步十进制加法计数器和三位扭环形计数器作为设计实例,经Hspice模拟与能耗分析证明,采用该方法设计的电路具有正确的逻辑功能,并能有效降低电路功耗,与已有方法设计的电路相比,能够节省更多的功耗或者提升电路性能.
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