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J4  2011, Vol. 45 Issue (6): 1032-1037    DOI: 10.3785/j.issn.1008-973X.2011.06.011
    
QCA circuit design of optimal universal logic gate ULG.2
based on modular methodology
XIAO Lin-rong1,2, CHEN Xie-xiong1, YING Shi-yan3
1. Department of Information and Electronic Engineering, Zhejiang University, Hangzhou 310028, China;
2. Department of Electrical and Electronic Engineering, Jiaxing University, Jiaxing 314001, China;
3. College of Information Engineering, Zhejiang University of Technology, Hangzhou 310032, China
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Abstract  

In order to reduce the number of wire-crossings in quantum-dot cellular automata (QCA) circuits and the types of QCA logic gates in logic synthesis, based on the introduction of basic principles of QCA , QCA logic devices and modular design methodology, a novel QCA optimal universal logic gate ULG.2 was designed. Three circuits of full adder/subtraction, full comparator and 4-to-1 multiplexer were implemented with the optimal QCA universal logic gate ULG.2. Simulation by using the QCADesigner tool for the proposed QCA circuits confirms that the proposed circuits have correct logic function and their performance was improved dramatically in comparison to the other previous designs. Especially, the proposed 4-to-1 multiplexer was reduced 31.8%QCA cells and 62.5% number of wire-crossings compared with the traditional design based on majority gates and inverters.



Published: 14 July 2011
CLC:  TN 432  
Cite this article:

XIAO Lin-rong, CHEN Xie-xiong, YING Shi-yan. QCA circuit design of optimal universal logic gate ULG.2
based on modular methodology. J4, 2011, 45(6): 1032-1037.

URL:

https://www.zjujournals.com/eng/10.3785/j.issn.1008-973X.2011.06.011     OR     https://www.zjujournals.com/eng/Y2011/V45/I6/1032


基于模块化技术的最佳ULG.2的QCA电路设计

为了减少纳米器件量子细胞自动机(QCA)电路的线交叉数和电路综合时采用的门电路类型,在介绍QCA细胞结构、逻辑器件、模块化设计技术以及最佳通用逻辑门ULG.2的基础上,提出基于模块化技术的最佳通用逻辑门ULG.2的QCA电路实现方案.利用最佳QCA通用逻辑门ULG.2设计了全加/减器、全比较器和4选1数据选择器.所设计的QCA电路均用QCADesigner软件进行模拟,结果表明:该电路不仅具有正确的逻辑功能,而且某些性能得到了很大的改善.特别地对于4选1数据选择器,与已有的多数门和反相器直接设计的电路相比,细胞数、QCA线交叉数分别减少了31.8%和62.5%.

[1] LENT C S, TOUGAW P D, BERNSTEIN G H, et al. Quantum cellular automata[J]. Nanotechnology, 1993, 4(1): 49-57.
[2] LENT C S, TOUGAW P D, POROD W. Bistable saturation in coupled quantum dots for quantum cellular automata[J]. Applied Physics Letters, 1993, 62(7): 714-716.
[3] MASSIMO MACUCC. Quantum cellular automata: theory, experimentation and prospects[M]. London: Imperial College Press, 2006.
[4] 王森,蔡理,郭律.基于量子细胞自动机的全加器实现[J].固体电子学研究与进展,2005,25(2): 148-151.
WANG Sen, CAI Li, GUO Lu. A novel full adder implementation using quantum cellular automata[J]. Research and Progress of SSE, 2005, 25(2): 148-151.
[5] YAU S S, TANG C K. Universal logic modules and their applications[J]. IEEE Transactions on Computers, 1970(C19): 141-149.
[6] CHEN X. The synthesis of combinational logic functions using ULM.3 universal circuit elements[J].The Radio and Electronic Engineer, 1983,53(3): 64-67.
[7] 潘张鑫,陈偕雄.或符合型通用逻辑门组合电路的故障检测[J].浙江大学学报:工学版,2007,41(8): 1260-1264.
PAN Zhangxin, CHEN Xiexiong. Faults detection in combinational circuits of OR Coincidence type universal logic gates\
[J\]. Journal of Zhejiang University: Engineering Science, 2007, 41 (8): 1260-1264.
[8] XIA Yinshui, QIU Keming. Design and application of universal logic gate based on quantumdot cellular automata[C]∥ The 11th International Conference on Communication Technologies 2008 (ICCT 2008). Hangzhou, China: IEEE, 2008: 335-338.
[9] BERZON D, FOUNTAIN T J. A memory design in QCAs using the SQUARES formalism[C]∥ Proceedings of the 9th Great Lakes Symposium on VLSI. Salt Lake, USA: IEEE Computer Society, 1999: 166-169.
[10] HUANG J, MOMENZADEH M, SCHIANO L, et al. Tilebased QCA design using majoritylike logic primitives[J]. ACM Journal on Emerging Technologies in Computing Systems, 2005, 1(3): 163-185.
[11] HUANG J, MOMENZADEH M, SCHIANO L, et al. Simulationbased design of modular QCA circuits[C]∥ Proceedings of 2005 5th IEEE Conference on Nanotechnology. Nagoya, Japan:IEEE, 2005(2): 533-536.
[12] 陈偕雄,沈继忠.近代数字理论[M].杭州:浙江大学出版社,2001.
[13]HELLERMANN L. A catalog of threevariable ORinvert and ANDinvert logical circuits[J]. IEEE Transactions on Electronic Computers, 1963(EC12): 198-223.
[14] QIU K M, XIA Y S. Quantumdots cellular automata comparator[C]∥ 2007 7th International Conference on ASIC Proceedings. Guilin, China: IEEE, 2007: 1297-1300.

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