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浙江大学学报(工学版)
J4  2012, Vol. 46 Issue (2): 333-337    DOI: 10.3785/j.issn.1008-973X.2012.02.024
    
A novel sample and hold circuit using clocked neuron-MOS scheme
HANG Guo-qiang1, LI Jin-xuan2, WANG Guo-fei2
1. School of Information and Electrical Engineering, Zhejiang University City College, Hangzhou, 310015, China;
2. Institute of Information and Communication Engineering, Zhejiang University, Hangzhou, 310027, China
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Abstract  

For converting a continuous-time signal into a discretetime signal, a new proposal for implementing voltage-mode sample and hold (S/H) based on clock-controlled neuronMOS scheme was presented. By employing the nMOS threshold compensation cell, the problem of threshold loss between the input voltage and the output voltage of a single neuron-MOS transistor-based source-follower, is solved, and thereby the accuracy of the S/H circuit is improved. Due to applying threshold compensation technique, the proposed S/H circuit is suitable for low-voltage operation. Besides, by utilizing a high-functionality clock-controlled neuronMOS device, the proposed S/H circuit has a considerable simpler structure and achieves higher power saving. A modified SPICE macro-model for clock-controlled neuron-MOS transistor was also presented in this paper, which can be used to analyze the circuit with variable preset voltage on the floating gate. The circuit is verified by HSPICE simulation with TSMC 0.35 μm double-polysilicon CMOS parameter, and a comparison is being made between the proposed S/H circuit and previously reported neuron-MOSbased ones. The simulation results show that the proposed circuit has low-power consumption and achieves significant improvement in sampling accuracy.

Published: 20 March 2012
CLC:  TN 432  
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Cite this article:

HANG Guo-qiang, LI Jin-xuan, WANG Guo-fei. A novel sample and hold circuit using clocked neuron-MOS scheme. J4, 2012, 46(2): 333-337.

URL:

http://www.zjujournals.com/eng/10.3785/j.issn.1008-973X.2012.02.024     OR     http://www.zjujournals.com/eng/Y2012/V46/I2/333


新型钟控神经元MOS采样/保持电路

为实现连续时间信号到离散时间信号的转换, 提出一种采用钟控神经元MOS管设计的新型电压型采样保持电路.在设计新方案中,通过引入nMOS阈值补偿单元,克服单管神经元MOS跟随器存在阈值损失这一缺点,提高采样保持电路的精度.采用具有高功能度的钟控神经元MOS管实现采样保持和跟随输出,使所设计的电路具有简单的结构和较低的功耗.对钟控神经元MOS管的SPICE宏模型进行改进,改进后的模型可用于对具有可变浮栅预置电压的电路进行分析.采用TSMC 0.35 μm双层多晶硅CMOS工艺参数对设计电路进行HSPICE模拟,并对新设计方案与现有采用神经元MOS管设计的采样保持电路进行比较.模拟结果表明,所提出设计方案明显提高了采样精度,并具有较低功耗.

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