Please wait a minute...
浙江大学学报(工学版)
自动化技术、信息技术     
多层图像叠加处理的低功耗自适应流水线设计
谭腾飞1,马德1,黄凯2,马琪1
1. 杭州电子科技大学 微电子CAD所,浙江 杭州 310018; 2.浙江大学 超大规模集成电路研究所,浙江 杭州 310027
Power-efficient image blending engine design based on self-adaptive pipeline
TAN Teng-fei1, MA De1, HUANG Kai2, MA Qi1
1. Microelectronic CAD Center, Hangzhou Dianzi University, Hangzhou 310018, China; 2. Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China
 全文: PDF(3492 KB)   HTML
摘要:

针对多层图像叠加处理技术的特点,提出低功耗自适应流水线及片上缓存架构,支持ITU-R BT.601和ITU-R BT.709标准下RGB和YCbCr格式的4层图像叠加显示.该架构根据各层图像格式,自适应调整流水线及各级逻辑工作状态以提高能效比.采用双向可控环形缓存,减少由于缓存状态导致的流水线停顿,保证流水线顺畅工作.采用像素选择性读取、色度空间转换(CSC)自适应等技术进一步降低功耗.实验结果表明:与其他相关设计相比,提出的流水线架构能够取得较好的处理效率和资源消耗比,在SMIC90工艺下硬件资源代价为136000门,工作频率达到150 MHz,能够满足3路1080p@30帧/s图像的实时叠加处理,最低动态功耗达到0.065 mW.

Abstract:

A power efficient self-adaptive pipeline and corresponding on-chip buffer architecture was proposed according to the characteristics of multi-image blending. The architecture supports four-image inputted with both RGB and YCbCr color format based on ITU-R BT.601 and ITU-R BT.709 standard. Depending on color format of each input image, the proposed blending engine automatically adapted pipeline architecture and work status of each stage to improve power efficiency. Bi-controllable circular buffer structure was adopted to decrease pipeline stalls, keeping pipeline smooth. Selective-fetching pixel and self-adaptive color space conversion techniques were adopted to reduce the power consumption. Experimental results show that the proposed work can achieve better tradeoff of power, area and performance compared with the related works. At the hardware cost of 136000 gate with SMIC90 technology, three-channel blending can be realized for 1080@30fp images in real time with 150 MHz frequency and the lowest power dynamic consumption can achieve 0.065 mW.

出版日期: 2018-06-06
:  TN 47  
通讯作者: 马德,男,讲师     E-mail: made@hdu.edu.cn
作者简介: 谭腾飞(1987-),男,硕士生,从事数字芯片IP设计与验证的研究.E-mail:tengfei_tan@163.com
服务  
把本文推荐给朋友
加入引用管理器
E-mail Alert
RSS
作者相关文章  

引用本文:

谭腾飞,马德,黄凯,马琪. 多层图像叠加处理的低功耗自适应流水线设计[J]. 浙江大学学报(工学版), 10.3785/j.issn.1008-973X.2015.01.005.

TAN Teng-fei, MA De, HUANG Kai, MA Qi. Power-efficient image blending engine design based on self-adaptive pipeline. JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), 10.3785/j.issn.1008-973X.2015.01.005.

链接本文:

http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2015.01.005        http://www.zjujournals.com/eng/CN/Y2015/V49/I1/27

[1] KIMMEL J, HAUTANEN J, LEVOLA T. Display technologies for portable communication device [C]∥ Proceedings of IEEE. [S. l.]: IEEE, 2002, 90(4): 581-590.
[2] 赵俊,张克环,李仁发. 嵌入式通用图形加速芯片的研究与设计[J]. 计算机工程与应用, 2008, 44(26): 74-76.
ZHAO Jun, ZHANG Ke-huan, LI Ren-fa. Research and design of embedded general in age enhancement chip [J]. Computer Engineering and Application, 2008, 44(26): 74-76.
[3] 周海燕. 片上LCD控制器中多层显示的设计与实现[D]. 南京: 东南大学, 2010: 18-41.
ZHOU Hai-yan. Design and implantation of a multi-layer LCD controller based on SoC [D]. Nanjing: Southeast University, 2010: 18-41.
[4] HOLM K, GUSTAFSS O. Low-complexity and low-power color space conversion for digital video [C]∥ Norchip Conference. Linkoping: [s. n.],2006: 179-182.
[5] LE T M, AKIE K, HORI T, et al. Three images blending engine supporting multicolor formats, various color depths with small-gates size and high-quality image for SoC design [C]∥ IEEE 8th International Conference on ASIC. Changsha: IEEE, 2009: 187-190.
[6] ITU-R Rec. BT.601-5. Studio encoding parameters of digital television for standard 4:3 and widescreen 16:9 aspect ratios [S]. [S. l.]: International Radio Consultative Committee, 1995.
[7] ITU-R Rec. BT.709-5. Parameter values for the HDTV standard for production and international programme exchange [S]. [S. l.]: International Radio Consultative Committee, 2002.
[8] PANTUWANG N, CHOTIKAKAMTHORN N. Alpha channel digital image watermarking method [C]∥ ICSP 2008. 9th International Conference on Signal Processing. Beijing: [s. n.], 2008: 880-883.
[9] RAFAEL C G. 数字图像处理[M]. 3版. 北京:电子工业出版社, 2011.
[10] INOUE K, NAKAMURA H, KAWAI H, et al. A 10Mb 3D frame buffer memory with Z-compare and alpha-blend units [C]∥Solid-State Circuits Conference. San Francisco: [s. n.], 1995: 302-303.
[11] XU K, CHOY C S, CHAN C F, et al. Power-efficient VLSI Implementation of bit stream parsing in H.264/AVC decoder [C]∥IEEE International Symposium on Circuits and Systems. Island of Kos: IEEE, 2006: 5339-5442.

[1] 陈超, 罗小华, 陈淑群, 俞国军. 基于现场可编程门阵列的高斯滤波算法优化实现[J]. 浙江大学学报(工学版), 2017, 51(5): 969-975.
[2] 蓝帆, 潘赟, 严晓浪, 宦若虹, CHENG Kwang ting. 片上网络良率评估的GPU加速[J]. 浙江大学学报(工学版), 2017, 51(1): 160-167.
[3] 夏凯锋,周小平,吴斌. 任意2k点存储器结构傅里叶处理器[J]. 浙江大学学报(工学版), 2016, 50(11): 2239-2244.
[4] 王树朋,黄凯,严晓浪. 基于遗传算法的覆盖率驱动测试产生器[J]. 浙江大学学报(工学版), 2016, 50(3): 580-588.
[5] 韩晓霞, 韩雁. 填充辅助多晶硅图形的参数成品率版图优化[J]. 浙江大学学报(工学版), 2015, 49(12): 2333-2339.
[6] 高史义, 罗小华, 卢宇峰, 刘富春, 张晨秋. 基于遗传算法的功能覆盖率收敛技术[J]. 浙江大学学报(工学版), 2015, 49(8): 1509-1515.
[7] 修思文, 李彦哲, 黄凯, 马德, 晏荣杰, 严晓浪. 面向MPSoC性能评估的高速缓存建模技术[J]. 浙江大学学报(工学版), 2015, 49(7): 1367-1375.
[8] 修思文, 黄凯, 余慜, 谢天艺, 葛海通, 严晓浪. 面向非写分配高速缓存的一致性协议及实现[J]. 浙江大学学报(工学版), 2015, 49(2): 351-359.
[9] 王钰博,黄凯,陈辰,冯炯,葛海通,严晓浪. 嵌入式Flash读取加速技术及实现[J]. 浙江大学学报(工学版), 2014, 48(9): 1570-1579.
[10] 修思文, 黄凯, 余慜, 谢天艺, 葛海通, 严晓浪. 面向非写分配高速缓存的一致性协议及实现[J]. 浙江大学学报(工学版), 2014, 48(9): 1-9.
[11] 黄凯杰, 黄凯, 马德, 王钰博, 冯炯, 葛海通, 严晓浪. 基于IP-XACT标准的SoC集成方法[J]. J4, 2013, 47(10): 1770-1776.
[12] 项晓燕,陈志坚,孟建熠,严晓浪. 基于邻行链接访问的低功耗指令高速缓存[J]. J4, 2013, 47(7): 1213-1217.
[13] 陈志坚,孟建熠,葛海通,严晓浪. 基于内存页面动态合并的旁路转换缓冲器设计[J]. J4, 2012, 46(1): 118-122.
[14] 张洋, 王秀敏, 陈豪威. 基于FPGA的低密度奇偶校验码编码器设计[J]. J4, 2011, 45(9): 1582-1586.
[15] 陈志坚,孟建熠,葛海通,严晓浪. 支持程序无缝切换的高性能硬件堆栈[J]. J4, 2011, 45(9): 1587-1592.