电信技术 |
|
|
|
|
任意2k点存储器结构傅里叶处理器 |
夏凯锋,周小平,吴斌 |
中国科学院 微电子研究所,北京 100029 |
|
Memory-based FFT processor for arbitrary 2k-point FFT computations |
XIA Kai feng, ZHOU Xiao ping, WU Bin |
Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China |
[1] PEASE M C. Organization of large scale Fourier processors [J]. Journal of the Association for Computing Machinery, 1969, 16(3): 474-482.
[2] COHEN D. Simplified control of FFT hardware [J]. IEEE Transactions on Acoustics, Speech and Signal Processing, 1976, 24(6): 577-579.
[3] JOHNSON L G. Conflict free memory addressing for dedicated FFT hardware [J]. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1992 39(5): 312-316.
[4] JO B G, SUNWOO M H. New continuousflow mixedradix (CFMR) FFT processor using novel inplace strategy [J]. IEEE Transactions on Circuits and Systems IRegular Papers, 2005, 52(5): 911-919.
[5] BAEK J, CHOI K. New address generation scheme for memorybased FFT processor using multiple radix2 butterflies [C]∥ 2008 International SoC Design Conference. Busan, Korea: IEEE, 2008, I273-276.
[6] TSAI P, LIN C, A Generalized conflictfree memory addressing scheme for continuousfow parallelprocessing FFT processors with rescheduling [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011, 19(12): 2290-2302.
[7] HUANG S, CHEN S, A highthroughput radix16 FFT processor with parallel and normal input/output ordering for IEEE 802153c systems [J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2012, 59(8): 1752-1765.
[8] CHO T, LEE H. A highspeed lowcomplexity modified radix25 FFT processor for high rate WPAN applications [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013, 21(1): 187-191.
[9] WANG C, YAN Y, FU X. A highthroughput low complexity radix2422 23 FFT/IFFT processor with parallel and normal input/output order for IEEE 802-11ad systems [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015, 23(11): 2728-2732.
[10] KIM E J, LEE J H, SUNWOO M H. Novel shared multiplier scheduling scheme for areaefficient FFT/IFFT processors [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015, 23(9): 1689-1699.
[11] YANG C H, YU T H, MARKOVIC D. Power and area minimization of reconfigurable FFT processors: A 3GPPLTE example [J]. IEEE Journal of SolidState Circuits , 2012, 47(3): 757-768.
[12] PENG S, SHR K, CHEN C et al. Energy-efficient 128 ~ 2048/1536-point FFT processor with resource block mapping for 3GPP-LTE system [C]∥2010 International Conference on Green Circuits and Systems. Shanghai, China: IEEE, 2010: 14-17.
[13] YU C, YEN M H. Areaefficient 128 2 048/1 536point pipeline FFT processor for LTE and mobile WiMaX systems [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015, 23(9): 1793-1800. |
|
Viewed |
|
|
|
Full text
|
|
|
|
|
Abstract
|
|
|
|
|
Cited |
|
|
|
|
|
Shared |
|
|
|
|
|
Discussed |
|
|
|
|