Low-jitter fast-locked 10.9−12.0 GHz charge-pump phase-locked loop

doi:10.3785/j.issn.1008-973X.2024.11.010

Journal of ZheJiang University (Engineering Science)

2024, Vol. 58

Issue (11): 2290-2298 DOI: 10.3785/j.issn.1008-973X.2024.11.010

Low-jitter fast-locked 10.9−12.0 GHz charge-pump phase-locked loop

Yongzheng ZHAN1(

),Rengang LI1,Tuo LI1,Xiaofeng ZOU1,Yulong ZHOU1,Qingsheng HU2,3,Lianming LI3

1. Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Limited Company, Jinan 250101, China
2. Institute of RF- and OE-ICs, Southeast University, Nanjing 210096, China
3. School of Information Science and Engineering, Southeast University, Nanjing 210096, China

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Abstract

A low-jitter high-speed charge-pump phase-locked loop (CPPLL) suitable for high-speed SerDes serial link was designed using 65 nm CMOS technology. Loop bandwidth and circuit structure of voltage-controlled oscillator (VCO), charge pump (CP), phase frequency detector (PFD) were optimized to reduce jitter caused by voltage ripple and internal noise. CPPLL can achieve a stable clock signal with the smaller jitter offset while meeting the wide frequency range and high speed requirements of SerDes link. Chip area including the entire pads is 0.309 mm². The measurement results show that CPPLL can generate a 10.9-12 GHz clock signal and exhibit a phase noise of ?111.47 dBc/Hz and a reference spur of ?25.14 dBc and a figure-of-merit (FoM) of ?223.5 dB at 10 MHz offset. It takes 600 μs to generate a stable 11.3 GHz clock signal, and its RMS jitter is 973.9 fs when the reference frequency is 706.25 MHz, which is approximately 0.065 UI. The power consumption is 47.3 mW at the supply voltage of 1.2 V. The proposed phase-locked loop (PLL) is suitable for high-speed communication link systems at 20 Gb/s and above.

Key words： voltage-controlled oscillator (VCO) charge pump low jitter serial link high speed

Received: 08 October 2023 Published: 23 October 2024

CLC:

TN 432

Fund: 山东省自然科学基金资助项目(ZR2022QF146)；山东省自然科学基金创新发展联合基金资助项目(ZR2023LZH004)；中国博士后科学基金资助项目(2024M751268).

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	Yongzheng ZHAN
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	Tuo LI
	Xiaofeng ZOU
	Yulong ZHOU
	Qingsheng HU
	Lianming LI

Cite this article:

Yongzheng ZHAN,Rengang LI,Tuo LI,Xiaofeng ZOU,Yulong ZHOU,Qingsheng HU,Lianming LI. Low-jitter fast-locked 10.9−12.0 GHz charge-pump phase-locked loop. Journal of ZheJiang University (Engineering Science), 2024, 58(11): 2290-2298.

URL:

https://www.zjujournals.com/eng/10.3785/j.issn.1008-973X.2024.11.010 OR https://www.zjujournals.com/eng/Y2024/V58/I11/2290

低抖动快锁定10.9~12.0 GHz电荷泵锁相环

基于65 nm CMOS 工艺，设计适用于高速SerDes串行链路的低抖动高速电荷泵锁相环(CPPLL)电路. 通过优化环路带宽以及压控振荡器（VCO）、电荷泵和鉴频鉴相器的电路结构, 抑制电压纹波和内部噪声引起的抖动, 以在满足SerDes链路需要的宽频范围和高速要求的同时, 电荷泵锁相环能够获得较小的抖动偏差和稳定的时钟信号. 包括整个焊盘在内的芯片面积为0.309 mm². 测试结果表明, 电荷泵锁相环能够实现10.9~12 GHz的输出时钟信号, 其在10 MHz频偏处的相位噪声、参考杂散和品质因数(FoM)分别为?111.47 dBc/Hz、?25.14 dBc和?223.5 dB. 当输入参考频率为706.25 MHz 时, CPPLL能够在600 μs后输出稳定的11.3 GHz时钟信号, 且RMS抖动为973.9 fs, 约为0.065 UI. 在电源电压为1.2 V下, 电路的功耗为47.3 mW. 所设计的锁相环（PLL）电路能够适用于20 Gb/s及以上的高速通信链路系统.

关键词： 压控振荡器(VCO), 电荷泵, 低抖动, 串行链路, 高速

Fig.1 Block diagram of DLL

Fig.2 Block diagram of LC-VCO CPPLL

Fig.3 Phase noise curve of LC-VCO CPPLL

Fig.4 Lock-time curve under different loop bandwidthes

Fig.5 Circuit diagram of complementary cross-coupled negative-resistance LC-VCO

Fig.6 Output waveform of VCO with cross-coupled transistor

Fig.7 Voltage-controlled characteristic curve of VCO under different corners

Fig.8 Phase noise of VCO

Fig.9 Circuit diagram of cascade-based CP

Fig.10 Characteristic curve of CP current matching

Fig.11 Circuit diagram of TSPC-based PFD

Fig.12 Charge process cascading PFD with CP

Fig.13 Leakage current curve of CP

Fig.14 Chip micrograph

Fig.15 Measurement platform of CPPLL

Fig.16 Frequency locking curve of CPPLL at 12.5 GHz for different corner

Fig.17 Jitter performance of CPPLL at SS corner

Fig.18 Transient measurement curve of CPPLL

Fig.19 Measurement curve of CPPLL phase noise

Fig.20 Measurement curve of CPPLL reference spur

Tab.1 Summary and comparison of CPPLL performance using 65 nm technology


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