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浙江大学学报(工学版)
浙江大学学报(工学版)  2021, Vol. 55 Issue (7): 1399-1406    DOI: 10.3785/j.issn.1008-973X.2021.07.019
信息与电子工程     
0~21 GHz高精度宽带硅基数字衰减器设计
刘美杉(),张为*(),郝东宁
天津大学 微电子学院，天津 300072
Design of 0~21 GHz wideband silicon-based digital attenuator with high accuracy
Mei-shan LIU(),Wei ZHANG*(),Dong-ning HAO
School of Microelectronics, Tianjin University, Tianjin 300072, China
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摘要：

针对射频前端收发系统中衰减结构宽带性能不稳定的问题，提出具有双重电容补偿的新型开关内嵌式衰减结构。该结构基于容性校正网络，在节约核心电路面积的同时通过调节零、极点对频率响应的影响，达到拓展衰减单元工作频带的目的，以满足跨频段、宽频域射频通信收发前端的设计需求. 基于HHNEC 0.18 μm SiGe BiCMOS工艺，采用新型电容补偿结构设计6位步进式数字衰减电路，该衰减器通过6位数控开关实现64种衰减状态，衰减步进0.5 dB，衰减范围0~31.5 dB. 仿真结果表明，在0~21 GHz工作频带内衰减误差均方根小于0.23 dB，附加相移均方根小于4.38°，插入损耗最大为?11.05 dB，最小为?4 dB，中心频率处1 dB压缩点17.3 dBm，核心电路版图面积0.86 mm×0.2 mm.
关键词： 数字步进式衰减器;  相控阵雷达;  高精度衰减;  低附加相移;  超宽带;  体悬浮技术    
Abstract:

A new switch embedded attenuator structure based on capacitive correction network was presented, in order to solve the problem of unstable broadband performance in the RF front-end transceiver system. The capacitive correction network saving the core circuit area by adjusting the influence of the zero and pole to the frequency response, expanded the working band, which satisfied the cross-band, wide frequency domain RF design requirements for communication transceiver front end. A 6-bit digital step attenuator with the correction network based on HHNEC 0.18 μm SiGe BiCMOS process was designed, the digital step attenuators had 6-bit digital control inputs with 64 attenuation states, the maximum attenuation of 31.5 dB and the least attenuation step of 0.5 dB. Simulation results show that in the bandwidth of 0~21 GHz, the 64-state root mean square (RMS) of attenuation error is less than 0.23 dB, the RMS of phase variation is less than 4.38°, the maximum insertion loss at 21 GHz is ?11.05 dB, the minimum insertion loss is ?4 dB, the 1 dB compression point at the center frequency is 17.3 dBm. The layout area of core circuit is 0.86 mm×0.2 mm.
Key words: digital step attenuator    phased array radar    high precision attenuation    low additional phase shift    ultra wide band    body-float technology
收稿日期: 2020-06-24 出版日期: 2021-07-05
CLC:  TN 433  
通讯作者: 张为     E-mail: ms03@tju.edu.cn;tjuzhangwei@tju.edu.cn
作者简介: 刘美杉（1995—），女，硕士生，从事射频模拟集成电路研究. orcid.org/0000-0002-8474-9304. E-mail： ms03@tju.edu.cn
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刘美杉
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引用本文:

刘美杉,张为,郝东宁. 0~21 GHz高精度宽带硅基数字衰减器设计[J]. 浙江大学学报(工学版), 2021, 55(7): 1399-1406.

Mei-shan LIU,Wei ZHANG,Dong-ning HAO. Design of 0~21 GHz wideband silicon-based digital attenuator with high accuracy. Journal of ZheJiang University (Engineering Science), 2021, 55(7): 1399-1406.

链接本文:

https://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2021.07.019    或    https://www.zjujournals.com/eng/CN/Y2021/V55/I7/1399

图 1  数字步进式开关内嵌衰减模块结构
图 2  简化小信号等效电路
图 3  4 dB桥T衰减幅度响应及零、极点分布
参数 单位 数值 参数 单位 数值
R1 Ω 44.00 RM1,on Ω 9.84
R2 Ω 38.00 CM1,off fF 43.36
R3 Ω 56.00 RM2,on Ω 23.00
Z0 Ω 50.00 CM2,off fF 20.66
表 1  4 dB桥T衰减单元器件参数
图 4  4 dB桥T衰减相位响应及零、极点分布
图 5  含有旁路电容补偿的4 dB桥T衰减结构零极点分布
图 6  含有旁路电容4 dB桥T衰减结构幅相响应
图 7  具有双电容补偿结构的衰减结构
图 8  2种电容补偿结构幅度响应对比
图 9  普通衰减单元与2种改进π型结构对比
图 10  浮体开关电路及深N阱剖面图
图 11  整体电路设计及最终版图
图 12  6位步进式衰减器仿真结果
设计结构 D/μm f/GHz RA/dB SA/dB IL/dB RL/dB RMSA'/dB RMSθ/（°） IP1dB/dBm S/mm2
*为核心电路面积
文献[5] 0.130 0~20 0~31.50 0.5 1.7-7.2 <?12 0.37 <4.0 10 0.14*（1.00×0.14）
文献[6] 0.350 14~18 0~31.50 0.5 8±0.6 <?10 0.29 <3.9 >10 0.27*（0.80×0.34）
文献[8] 0.180 3~22 0~31.00 1 5.53~13.07 <?11 0.53 <6.3 18.4 —
文献[10] 0.130 3~13 0~31.75 0.25 <6.6 <?9 0.17 <2.8 16.8 1.57（1.59×0.79）
文献[19] 0.065 8~18 0~31.50 0.5 6.1~8.6 <?10 0.1 <5.5 12 0.273*（0.91×0.3）
文献[20] 0.180 0~18 0~31.50 0.5 2.9~6.1 <?11 0.39 <2.4 — —
本文 0.180 0~21 0~31.50 0.5 4~11.05 <?8.35 0.23 <4.38 17.3 0.172*（0.86×0.02）
表 2  电容补偿结构衰减器关键性能对比
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