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浙江大学学报(工学版)  2018, Vol. 52 Issue (9): 1796-1803    DOI: 10.3785/j.issn.1008-973X.2018.09.021
朱涛涛1, 项晓燕2, 陈晨2, 孟建熠2, 严晓浪1
1. 浙江大学 电气工程学院, 浙江 杭州 310027;
2. 复旦大学 微电子学院, 上海 201203
Timing error resilient clock gate design for wide-voltage application
ZHU Tao-tao1, XIANG Xiao-yan2, CHEN Chen2, MENG Jian-yi2, YAN Xiao-lang1
1. College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China;
2. College of Microelectronics, Fudan University, Shanghai 201203, China
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为了将时钟门控技术应用于时序容错系统中,提出具备时序错误检测与自纠正能力的时钟门控单元.该单元通过监测内部虚拟节点电压变化,得到数据晚到信息;利用该监测信息可以重新打开时钟树网络,完成时钟被错误关断情形的当前周期自主现场纠错.给出容错时钟门控单元在现有的多种时钟门控技术中的适用性分析,讨论与之对应的纠错方案选择策略.基于SMIC 40 nm LL工艺库,仅新增12个额外的晶体管实现该单元,从原理图和版图2个层面,对其在宽电压工作下的容错能力进行分析验证,并给出集成到系统设计时所需的时序检查方法.将该单元应用于一款商用处理器C-SKY CK802物理设计中,实验结果表明系统能效相对于传统设计提高了64.7%,而时钟树功耗相对于现有的容错设计下降了32%.


A clock gate cell with timing error detection and self-correction mechanism was proposed to introduce clock gating technique to error resilient system. Data's late arriving information was obtained through monitoring the voltage change of the inner virtual node, with which the clock network was enabled again and the in-field error correction current cycle when the clock was turned off by mistake was accomplished. Meanwhile, the applicability in different clock gating techniques was discussed with the corresponding error correction strategy. Based on SMIC 40 nm LL library, the cell only required twelve additional transistors compared to the traditional one. The ability of error resilience in wide-voltage operation is verified through the schematic layout; the timing constraints analysis method in the cell integration is given. It is embedded into a commercial C-SKY CK802 processor and the simulation results show that energy efficiency improves by 64.7% compared with traditional design; clock tree power decreases by 32% over current error resilient design.

收稿日期: 2017-02-14 出版日期: 2018-09-20
CLC:  TN432  


通讯作者: 项晓燕,女,讲师     E-mail: 项晓燕,女,讲师
作者简介: 朱涛涛(1990-),男,博士生.从事处理器架构与低功耗时序容错电路研究
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朱涛涛, 项晓燕, 陈晨, 孟建熠, 严晓浪. 面向宽电压应用的容错时钟门控单元设计[J]. 浙江大学学报(工学版), 2018, 52(9): 1796-1803.

ZHU Tao-tao, XIANG Xiao-yan, CHEN Chen, MENG Jian-yi, YAN Xiao-lang. Timing error resilient clock gate design for wide-voltage application. JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), 2018, 52(9): 1796-1803.


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