[1] KWON I, KIM S, FICK D, et al. Razor-lite:a light-weight register for error detection by observing virtual supply rails[J]. IEEE Journal of Solid-State Circuits, 2014, 49(9):2054-2066.
[2] 张苏敏, 陈黎明, 袁甲, 等. 面向亚阈值的脉冲生成电路设计[J]. 微电子学与计算机, 2014(9):118-121 ZHANG Su-min, CHEN Li-ming, YUAN Jia, et al. Design of subthreshold pulse generator[J]. Microelectronics & Computer, 2014(9):118-121
[3] HUANG C M, LIU T T, CHIUEH T D. An energy-efficient resilient flip-flop circuit with built-in timing-error detection and correction[C]//2015 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). Hsinchu:IEEE, 2015:1-4.
[4] SHIN I, KIM J J, LIN Y S, et al. One-cycle correction of timing errors in pipelines with standard clocked elements[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(2):600-612.
[5] VALADIMAS S, FLOROS A, TSIATOUHAS Y, et al. The time dilation technique for timing error tolerance[J]. IEEE Transactions on Computers, 2014, 63(5):1277-1286.
[6] CHAE K, MUKHOPADHYAY S. A dynamic timing error prevention technique in pipelines with time borrowing and clock stretching[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2014, 61(1):74-83.
[7] ZHANG Y, KHAYATZADEH M, YANG K, et al. 8.8 irazor:3-transistor current-based error detection and correction in an arm cortex-r4 processor[C]//2016 IEEE International Solid-State Circuits Conference (ISSCC). San Francisco:IEEE, 2016:160-162.
[8] FUKETA H, HASHIMOTO M, MITSUYAMA Y, et al. Adaptive performance compensation with in-situ timing error predictive sensors for subthreshold circuits[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012, 20(2):333-343.
[9] CHOUDHURY M, CHANDRA V, MOHANRAM K, et al. TIMBER:Time borrowing and error relaying for online timing error resilience[C]//Design, Automation & Test in Europe Conference & Exhibition (DATE), . Dresden:IEEE, 2010:1554-1559.
[10] SHIN I, KIM J J, LIN Y S, et al. A pipeline architecture with 1-cycle timing error correction for low voltage operations[C]//Proceedings of the 2013 International Symposium on Low Power Electronics and Design. Beijing:IEEE Press, 2013:199-204.
[11] ZHANG J, YUAN F, YE R, et al. Forter:A forward error correction scheme for timing error resilience[C]//2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). San Jose:IEEE, 2013:55-60.
[12] WIMER S, KOREN I. Design flow for flip-flop grouping in data-driven clock gating[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 22(4):771-778.
[13] CONSTANTIN J, WANG L, KARAKONSTANTIS G, et al. Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment[C]//Design, Automation & Test in Europe Conference & Exhibition (DATE), . Grenoble:IEEE, 2015:381-386.
[14] BHUTADA R, MANOLI Y. Complex clock gating with integrated clock gating logic cell[C]//International Conference on Design & Technology of Integrated Systems in Nanoscale Era. DTIS. Rabat:IEEE, 2007:164-169.
[15] ZHANG Y, TONG Q, LI L, et al. Automatic register transfer level CAD tool design for advanced clock gating and low power schemes[C]//2012 International SOC Design Conference (ISOCC). Jeju:IEEE, 2012:21-24.
[16] 阳玉才. DisplayPort数字视频设计与研究[D]. 合肥:合肥工业大学, 2012. YANG Yu-cai. Design and research on displayport digital video interface[D]. Hefei:HeFei University of Technology, 2012.
[17] UPPU R K, UPPU R T, SINGH A D, et al. Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths[C]//201427th International Conference on VLSI Design and 201413th International Conference on Embedded Systems. Mumbai:IEEE, 2014:133-138.
[18] YANG Y M, JIANG I H R, HO S T. PushPull:Short-path padding for timing error resilient circuits[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2014, 33(4):558-570.
[19] LAULAINEN E, TURNQUIST M J, MÄKIPÄÄ J, et al. subthreshold timing-error detection 8 bit microcontroller S[C]//2012 IEEE International Symposium on Circuits and Systems(ISCAS). Seoul:IEEE, 2012:2953-2956.
[20] C-SKY Microsystems. CK802 of C-SKY embedded CPU:8-Bit CPU cost, 32-Bit CPU efficiency[EB/OL].[2017-02-14]. http://en.c-sky.com/solution/13411.htm.
[21] BOWMAN K A, TSCHANZ J W, KIM N S, et al. Energy-efficient and metastability-immune timing-error detection and instruction-replay-based recovery circuits for dynamic-variation tolerance[C]//Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International. San Francisco:IEEE, 2008:402-623.
[22] DAS S, TOKUNAGA C, PANT S, et al. RazorⅡ:in situ error detection and correction for PVT and SER tolerance[J]. IEEE Journal of Solid-State Circuits, 2009, 44(1):32-48.
[23] KIM S, SEOK M. Variation-tolerant, ultra-low-voltage microprocessor with a low-overhead, within-a-cycle in-situ timing-error detection and correction technique[J]. IEEE Journal of Solid-State Circuits, 2015, 50(6):1478-1490. |