| 计算机技术﹑电信技术 | 
									
										
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    					| 面向非写分配高速缓存的一致性协议及实现 | 
  					 
  					  										
						| 修思文1, 黄凯1, 余慜1, 谢天艺1, 葛海通2, 严晓浪1 | 
					 
															
					| 1. 浙江大学 超大规模集成电路研究所,浙江 杭州 310027;2. 杭州中天微系统有限公司,浙江 杭州 310027 | 
					 
										
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    					| Cache coherence protocol and implementation for multiprocessors with no-write-allocate caches | 
  					 
  					  					  					
						| XIU Si-wen1, HUANG Kai1, YU Min1, XIE Tian-yi1,GE Hai-tong2, YAN Xiao-lang1 | 
					 
															
						| 1. Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China; 2. Hangzhou C-SKY Microsystems Co., Ltd, Hangzhou 310027,  China | 
					   
									 
				
				
					
						
							
								
									
									
									
									
									 
          
          
            
             
												
												
												
												
												
												引用本文: 
																													
																																修思文, 黄凯, 余慜, 谢天艺, 葛海通, 严晓浪. 面向非写分配高速缓存的一致性协议及实现[J]. 浙江大学学报(工学版), 10.3785/j.issn.1008-973X.2015.02.023.
																															 
																																								     												                                                    																													
																																XIU Si-wen, HUANG Kai, YU Min, XIE Tian-yi,GE Hai-tong, YAN Xiao-lang. Cache coherence protocol and implementation for multiprocessors with no-write-allocate caches. JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), 10.3785/j.issn.1008-973X.2015.02.023.
																															  
																												
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																	http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2015.02.023
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																http://www.zjujournals.com/eng/CN/Y2015/V49/I2/351
														    
														   
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[10] HACKENBERG D, MOLKA D, NAGEL W E. Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems [C]∥ Proceedings of the 42Nd Annual IEEE/ACM International Symposium on microarchitecture. New York: IEEE, 2009: 413-422. 
[11] PONG F, DUBOIS M. Formal automatic verification of cache coherence in multiprocessors with relaxed memory models [J]. IEEE Transactions on Parallel and Distributed Systems, 2000, 11(9): 989-1006. 
[12] C-SKY Microsystems Co., Ltd. CK600 Introduction [EB/OL].[2014-01-11]. http:∥www.c-sky.com/downdisp.php?aid=72 
[13] Micron Technology, Inc. MT48LC32M16A2 datasheet [EB/OL].[2014-01-11]. http:∥www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/512Mb_sdr.pdf 
[14] Embedded Microprocessor Benchmark Consortium. MultiBenchTM 1.0 Benchmark Software [EB/OL]. [2014-01-11]. http:∥www.eembc.org/benchmark/multi_sl.php  | 
															   
																													 
									             
									           
             
			            			 
			 
             
												
											    	
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