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Journal of ZheJiang University (Engineering Science)  2022, Vol. 56 Issue (5): 1035-1043    DOI: 10.3785/j.issn.1008-973X.2022.05.021
    
Monolithic integrated resonant boost converter design
Zi-heng LIU(),Fan-yi MENG*(),Chen-fei WANG,Kai-xue MA
School of Microelectronics, Tianjin University, Tianjin 300072, China
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Abstract  

A three-dimensional integrated single-switch full-resonant boost converter was proposed based on silicon on insulator (SOI) process platform and gallium nitride (GaN) power transistors, in order to solve the problem of low power density of resonant power converters operating at high frequency. The switching frequency was 500 MHz. The main body of the converter adopted the derivative circuit structure of the traditional Class-E amplifier, i. e. parallel Class-E topology, and the gate driver adopted the single-switch resonant driving topology. The resonant inductance components in the converter were realized by the planar spiral inductor provided in the SOI process, the resonant capacitance components were realized by the Miller parasitic capacitance of the GaN power transistor, and the silicon-based chip and the GaN chip were connected by three-dimensional flip-chip technology. A detailed analysis was carried out around the design of circuit parameters, the realization of resonant components and the design of layout structure. Experimental results showed that when the input voltage was 12 V, the highest power density of the on-chip converter was 1.481W/mm2, the full-load efficiency was 60%, and the highest efficiency was 89%. This design provides a new idea for realizing power converter with high power density and high integration.



Key wordsresonant power converter      3D integration      circuit design      power density      conversion efficiency     
Received: 12 December 2021      Published: 31 May 2022
CLC:  TN 432  
Fund:  国家重点研发计划资助项目(2019YFB1803200)
Corresponding Authors: Fan-yi MENG     E-mail: zihengliu@tju.edu.cn;mengfanyi@tju.edu.cn
Cite this article:

Zi-heng LIU,Fan-yi MENG,Chen-fei WANG,Kai-xue MA. Monolithic integrated resonant boost converter design. Journal of ZheJiang University (Engineering Science), 2022, 56(5): 1035-1043.

URL:

https://www.zjujournals.com/eng/10.3785/j.issn.1008-973X.2022.05.021     OR     https://www.zjujournals.com/eng/Y2022/V56/I5/1035


单片集成谐振式升压转换器设计

为了解决高频谐振功率转换器功率密度较低的问题,提出基于绝缘体上硅(SOI)工艺平台和氮化镓(GaN)功率晶体管的三维集成的单开关全谐振升压转换器,开关频率为500 MHz. 转换器主体采用传统Class-E放大器的衍生电路结构?并联式Class-E拓扑,栅极驱动器采用单管谐振式驱动拓扑. 转换器中的谐振电感元件采用SOI工艺中提供的平面螺旋电感实现,谐振电容元件采用GaN功率晶体管的米勒寄生电容实现,硅基芯片与GaN芯片通过三维倒装技术连接. 围绕电路参数设计、谐振元件的实现和版图结构设计进行详细分析. 实验结果显示,当输入电压为12 V时,片上转换器的最高功率密度为1.481 W/mm2,满载效率为60%,最高效率为89%. 本设计为实现高功率密度、高集成度的功率转换器提供了新思路.


关键词: 谐振式功率转换器,  三维集成,  电路设计,  功率密度,  转换效率 
Fig.1 Layout of symmetrical spiral inductor PSI2 and its inductance and quality factor versus operating frequency
Fig.2 Layout of symmetrical spiral inductor and its inductance and quality factor versus operating frequency
Fig.3 Cross-sectional sketch view of silicon based SOI process and size information of GaN device (EPC2036)
Fig.4 Schematic diagram of full resonant parallel Class-E converter
Fig.5 Max output voltage swing of resonant gate driver under different source voltage
Fig.6 Voltage gain and amplitude of resonant current versus f2/f0 of resonant tank
Fig.7 Analysis model of inverter stage circuit in parallel Class-E converter
Fig.8 Relationship between VDS and characteristic impedance of L1-C1 with resonant frequency of L1-C1 lower than switching frequency
Fig.9 Relationship between VDS and characteristic impedance of L1-C1 with resonant frequency of L1-C1 higher than switching frequency
变量 数值 备注
Lr/nH 2.81 PSI2电感器,R = 400 μm
L1/nH 8.1 PSI3电感器,R = 500 μm
L2/nH 1.73 PSI2电感器,R = 475 μm
C1/pF 75 GaN HEMT寄生电容
C2/pF 75 GaN HEMT寄生电容
Tab.1 Values and types of components in driver stage circuit and power stage circuit
(mA·μm?1)
金属层 Amax
Tm=85 ℃ Tm=110 ℃ Tm=125 ℃
M1 5.88 1.34 1.14
M2、M3 7.94 1.81 1.14
M4、M5 77.48 17.63 11.08
Pad 31.64 7.20 3.23
Tab.2 Max linear electric current density of every metal layer at temperature of 85 ℃, 110 ℃ and 125 ℃
Fig.10 Placement and screen of layout of converter
Fig.11 Simulated Vgs and VDS waveforms at different load resistance values
Fig.12 Simulated output voltage waveforms and ripples at different load resistance values
Fig.13 Output voltage and conversion efficiency versus load resistance
Fig.14 Compositions and percentages of power consumption of converter
设计 f/MHz 拓扑 VOUT/VIN 工艺 Pden/(W·mm?2 A/mm2 η/%
本研究 500.0 并联Class-E 12.0 V/20.0 V 130 nm SOI+GaN 1.480 9.00 60
Burkhart等[5] 75.0 并联Class-E 12.0 V/30.0 V PCB 0.012 ? 87
Liu等[15] 300.0 并联Class-E 12.0 V/18.0 V IPD+GaN 0.048 92.00 47
Pilsoon等[1] 680.0 开关电感 12.0 V/20.0 V GaN-on-SiC 0.240 9.00 39
Mclaughln等[19] 47.5 开关电容 4.4 V/2.2 V 180 nm CMOS 0.097 8.93 75
Nghia等[20] 450.0 开关电容 1.2 V/0.6 V 65 nm CMOS 0.730 0.65 78
Tab.3 Index comparison between proposed design and other related design
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