Please wait a minute...
J4  2013, Vol. 47 Issue (11): 2025-2030    DOI: 10.3785/j.issn.1008-973X.2013.11.021
    
A novel time error calibration technique for DACs
SHI Qi-feng, XUE Xiao-bo, HE Le-nian
Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China
Download:   PDF(0KB) HTML
Export: BibTeX | EndNote (RIS)      

Abstract  

A time error calibration technique based on time measurement circuit (TMC) was presented in this paper to improve the dynamic performance of digital-to-analog convertor (DAC). The TMC included time amplifier (TA) and time-to-digital convertor (TDC). By using TA to linearly amplify the time error before TDC converting it into corresponding digital value, the calibration technique realized detection and quantization of the time error. According to the digital value, the time error was erased by using the delay circuit. The simulation results show that the calibration technique can detect time error less than 500 fs in 3 to 4 periods. While applying the technique to a 12-bit 500 MSPS current-steering DAC, the spurious free dynamic range (SFDR) of the output in full Nyquist band increases 6 dB averagely and 10 dB maximally.



Published: 01 November 2013
CLC:  TN 401  
Cite this article:

SHI Qi-feng, XUE Xiao-bo, HE Le-nian. A novel time error calibration technique for DACs. J4, 2013, 47(11): 2025-2030.

URL:

http://www.zjujournals.com/eng/10.3785/j.issn.1008-973X.2013.11.021     OR     http://www.zjujournals.com/eng/Y2013/V47/I11/2025


新型数模转换器时域误差校正方法

为了提高数模转换器的动态性能,提出一种基于时间检测器的时域误差校正方法.时间检测器包含时间差放大器和时数转换器,时间差放大器对时域误差进行线性放大,将放大后的时域误差经由时数转换器转化为数字量,实现对时域误差的检测与量化,并利用延时电路根据量化值对时域误差进行校正.仿真结果表明,该校正方法可以在3到4个校正周期内检测出小于500 fs的时域误差;将该校正方法应用于一个12位500 MSPS的电流舵数模转换器时,输出信号在全奈奎斯特带宽内的无杂波动态范围平均提高了6 dB,最大提升幅度达到10 dB.

[1] CHEN Tao, GIELEN G. The analysis and improvement of a current-steering DACs dynamic SFDR-I: the cell-dependent delay differences [J]. IEEE Transactions on Circuit and Systems-I, 2006, 53(1):3-15.
[2] BECHTHUM E, TANG Yong-jian, HEGT H, et al. Timing error measurement for highly linear wideband digital to analog converters [C]∥ IEEE International Symposium on Circuit and Systems (ISCAS). Rio de Janeiro: IEEE, 2011: 2019-2022.
[3] TANG Yong-jian, HEGT H, ROERNUND A. DDL-based calibration techniques for timing errors in current-steering DACs [C]∥ IEEE International Symposium on Circuit and Systems (ISCAS). Island of Kos: IEEE, 2006: 101-104.
[4] TANG Yong-jian, BRIAIRE J, DORIS K, et al. A 14 bit 200MS/s DAC with SFDR>78dBc, IM3<-83dBc and NSD<-163dBm/Hz across the whole nyquist band enabled by dynamic-mismatch mapping [J]. IEEE Journal of Solid-State Circuit, 2011, 46(6): 1372-1381.
[5] ABAS M A, RUSSEL G, KINNIMENT D J. Design of sub-10-picoseconds on-chip time measurement circuit [C]∥ Design, Automation and Test in Europe Conference and Exhibition. Paris: IEEE, 2004: 804-809.
[6] ABAS M A, BYSTROV A, KNNIMENT D J, et al. Time difference amplifier [J]. Electronics Letters, 2002, 38(33): 1437-1438.
[7] JANSSON J, MANTYNIEMI A, KOSTAMOVAARA J. A CMOS time-to-digital converter with better than 10ps single-shot precision [J]. IEEE Journal of Solid-State Circuits, 2006, 41(6): 1286-1296.
[8] DUDEK P, SZCZEPANSKI S, HATFIELD J. A high-resolution CMOS time-to-digital converter utilizing a vernier delay line [J]. IEEE Journal of Solid-State Circuits, 2000, 35(2): 240-247.
[9] TRAFF H. Novel approach to high speed CMOS current comparators [J]. Electronics Letters, 1992, 28(3): 310-312.
[10] LEE M, ABIDI A. A 9b 1.25ps Resolution coarse-Fine time-to-digital converter in 90nm CMOS that amplifies a time residue [C] ∥ 2007 Symposium on VLSI Circuits Digest of Technical Papers. Kyoto: IEEE, 2007: 168-169.

[1] SUN Ke-xu, HE Le-nian. A calibration technique based on frequency-domain characteristics for pipelined ADCs[J]. J4, 2013, 47(8): 1393-1402.
[2] LU Yan-feng, HE Le-nian, CHEN Jun-xiao, WANG Xuan. Frequency compensation of high-gain four-stage operational amplifier[J]. J4, 2010, 44(11): 2137-2141.