|
|
Frequency compensation of high-gain four-stage operational amplifier |
LU Yan-feng, HE Le-nian, CHEN Jun-xiao, WANG Xuan |
Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China |
|
|
Abstract A new frequency compensation topology was proposed to improve the properties of four-stage opamp’s stabilization and unity-gain bandwidth's widening. The multipath nested miller compensation (MNMC) was used to split a left-half-plane zero and a right-half-plane zero, and the frequency compensation was simplified by zero-pole cancellation with a new leftplane pole created by an additional feed-forward path. Pushing the nondominant poles to high frequency with reasonable arrangement of their locations relative to unity-gain bandwidth not only helped the stabilization of the opamp, but also widened unity-gain bandwidth. The opamp was designed and implemented by using TSMC’s 0.25 μm CMOS mixed signal technology, the simulation and test results indicate that it only need power of 0.842 mW and die area of 150 mm2. It achieve 2.42 MHz unity-gain bandwidth with phase margin of 60.15° and more than 150 dB DC gain under 3.6 V supply voltage.
|
Published: 23 December 2010
|
|
高增益四级运放频率补偿技术
为改善四级运放不易稳定和单位增益带宽较窄的特性,提出一种新的四级运放频率补偿技术.采用多路嵌套式密勒补偿技术,实现左半平面零点和右半平面零点分离,并通过额外增加一条前馈通路产生左半平面零点,抵消了一个极点,简化了四级运放的频率补偿问题.通过将次极点向高频的推移以及次极点和单位增益带宽比例大小的合理设计,不仅保证了运放的稳定,同时增大了运放的单位增益带宽.经台积电 (TSMC)0.25 μm 互补金属氧化物半导体(CMOS)混合信号工艺仿真和流片测试结果显示,该四级运放仅消耗0.842 mW功耗,0.150 mm2的芯片面积,在3.6 V电源电压下具有60.15°的相位裕度,2.42 MHz的单位增益带宽,大于150 dB的直流增益.
|
|
[1] ENZ C C, TEMES G C. Circuit techniques for reducing the effects of opamp imperfections: autozeroing, correlated double sampling and chopper stabilization [J]. Proceedings of the IEEE, 1996, 84(11):1584-1614.
[2] GRASSO A D, PALUMBO G, PENNISI S. Active reversed nested Miller compensation for threestage amplifiers[C]∥Proceedings of ISCAS 2006. Island of Kos, Greece: [s.n.], 2006:911-914.
[3] PERNICI S, NICOLLINI G, CASTELLO R. A CMOS lowdistortion fully differential power amplifier with double nested Miller compensation[J]. IEEE Journal SolidState Circuits, 1993, 28(7):758-763.
[4] KA N L, MOK P K, WING H K. Righthalfplane zero removal technique for lowvoltage lowpower nested Miller compensation CMOS amplifier[C]∥Proceedings of ICECS 1999. Cyprus: [s.n.],1999:599-602.
[5] YOU F, EMBABI, S H K, SANCHEZ S E. Multistage amplifier topologies with nested GmC compensation [J]. IEEE Journal SolidState Circuits, 1997, 32(12):2000-2011.
[6] KA N L, MOK P K T. Analysis of multistage amplifierfrequency compensation[J]. IEEE transactions on circuits and systems I: fundamental theory and applications, 2001, 48(9):1041-1056.
[7] GIUSTOLIS G, PALUMBO G. An approach to test the openloop parameters of feedback amplifiers [J]. IEEE transactions on circuits and systems I: fundamental theory and applications, 2002, 49(1):70-75. |
|
Viewed |
|
|
|
Full text
|
|
|
|
|
Abstract
|
|
|
|
|
Cited |
|
|
|
|
|
Shared |
|
|
|
|
|
Discussed |
|
|
|
|