［1］ IIZUKA K, MATSUI H, UEDA M, et al. A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40MS/s ［J］. IEEE Journal of Solid-State Circuits, 2006, 41(4): 883-890.

［2］ MING J, LEWIS S H. An 8-bit 80Msample/s pipelined analog-to-digital converter with background calibration ［J］. IEEE Journal of Solid-State Circuits, 2001, 36(10): 1489-1497.

［3］ SHU Y S, SONG B S. A 15-bit linear 20-MS/s pipelined ADC digitally calibrated with signal-dependent dithering ［J］. IEEE Journal of Solid-State Circuits, 2008, 43(2): 342-350.

［4］ MASSOLINI R G, CESURA G, CASTELLO R. A fully digital fast convergence algorithm for nonlinearity correction in multistage ADC ［J］. IEEE Trans. Circuits Syst. II, Express Briefs, 2006, 53(5): 389-393.

［5］ SUN K, HE L. Parallel background calibration with signal-shifted correlation for pipelined ADC ［C］∥ IEEE 13th International Symposium on Integrated Circuits. Singapore: IEEE, 2011, 11: 340-343.

［6］ SUN K, HE L. A fast combination calibration of foreground and background for pipelined ADCs ［J］. Journal of Semiconductors, 2012, 33(6): 1-11.

［7］ MURMANN B, BOSER B. A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification ［J］. IEEE Journal of Solid-State Circuits, 2003, 38(12): 2040-2050.

［8］ MURMANN B. Digital calibration for low-power high-performance A/D conversion ［D］. Berkeley: University of California Berkeley, 2003.

［9］ PENG B, LI H, LEE S C, LIN P F , et al. A virtual-ADC digital background calibration technique for multistage A/D conversion ［J］. IEEE Trans. Circuits Syst. II, Express Briefs, 2010, 57(11): 853-857.

［10］ PENG B, HUANG G Z, LI H, et al. A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS ［C］∥ IEEE Custom Integrated Circuits Conference (CICC). San Jose: IEEE, 2011: 1-4.

［11］ YUAN J, FUNG S W, CHAN K Y, XU R. A 12-bit 20 MS/s 56.3 mW pipelined ADC with interpolation-based nonlinear calibration ［J］. IEEE Trans. Circuits Syst. I, Regular Papers, 2011, 59(3): 555-565.

［12］ VAN DE VEL H, BUTER B A J, VAN DER PLOEG H, et al. A 1.2-V 250-mW 14-b 100-MS/s digitally calibrated pipeline ADC in 90-nm CMOS ［J］. IEEE Journal of Solid-State Circuits, 2009, 44(4): 1047-1056.

［13］ SANSEN W. Distortion in elementary transistor circuits ［J］. IEEE Trans. Circuits Syst. II, 1999, 46(3): 315-325.

［14］ KAZMI S M R, GOTO H, GUO H J, et al. A Novel algorithm for fast and efficient speed-sensorless maximum power point tracking in wind energy conversion systems ［J］. IEEE Transactions on Industrial Electronics, 2011, 58(1): 29-36.