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浙江大学学报(工学版)
J4  2011, Vol. 45 Issue (7): 1206-1214    DOI: 10.3785/j.issn.1008-973X.2011.07.011
    
Mixed increasing filter pipeline design for H.264/AVC deblocking filter
MA De1, HUANG Kai1, CHEN Hua-feng2, YU Min1, YAN Xiao-lang1
1. Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China;
2. College of Electronic and Information, Zhejiang Institute of Media and Communications, Hangzhou 310018, China
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Abstract  

A mixed increasing filter pipeline and its on-chip memory architecture were proposed in order to address the challenges of main-profile deblocking filter. The filter adopts mixed increasing filtering order for main-profile deblocking filter and uses six-stage pipeline for parallel filtering on target pixels. The memory architecture can efficiently support both row/column and frame/field data access in main-profile filter. Then pipeline stall and off-chip DRAM access were reduced by improving the granularity of data reusability. Experimental results show that the architecture can achieve better tradeoff between hardware cost and performance improvement compared with the related works. At the hardware cost of 25.7K gate cell and 768 Byte SRAM, three parallel real time deblocking filter for 1080P HDTV H.264 main-profile video stream can be realized.

Published: 01 July 2011
CLC:  TN 919.8  
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Cite this article:

MA De, HUANG Kai, CHEN Hua-feng, YU Min, YAN Xiao-lang. Mixed increasing filter pipeline design for H.264/AVC deblocking filter. J4, 2011, 45(7): 1206-1214.

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https://www.zjujournals.com/eng/10.3785/j.issn.1008-973X.2011.07.011     OR     https://www.zjujournals.com/eng/Y2011/V45/I7/1206


H.264去块效应滤波器的混合递增滤波流水线设计

针对H.264/AVC主要档次去块效应滤波器的特点,提出一种混合递增的滤波流水线及片上存储架构.采用混合递增的去块效应滤波顺序,通过6级流水线实现像素点的并行滤波.该流水线的存储器架构可以有效支持主要档次的行/列和帧/场数据访问模式,利用滤波数据的相关性提高重用粒度,减少流水线阻塞和片外DRAM的访问.实验结果表明：与其他相关工作比较,流水线架构能够取得较好的性能和资源消耗比,在25.7K门和768Byte SRAM的硬件资源代价下,可以实现3路1080P HDTV的H.264主要档次视频实时去块效应滤波.

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