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| Design methodology of FPGA based reconfigurable video encoder |
| DU Juan, DING Dan-dan, YU Lu |
Institute of Information and Communication Engineering, Zhejiang University,
Zhejiang Provincial Key Laboratory of Information Network Technology, Hangzhou 310027, China |
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Abstract Field programmable gate array (FPGA) based reconfigurable video encoder was presented in this paper. In order to enhance the system throughout and facilitate Function unit (FU) reusability and extensibility, a hierarchical FU partition method with multiple granularities is proposed. For simplicity in reconfiguration and complexity reduction, we adopt different storage structure as the way of connecting data. Based on the proposed methods, an efficient architecture for I-frame video encoder supporting H.264/AVC and AVS was realized. As a result, the proposed architecture can be easily reconfigured to satisfy 25 (37) frames per second encoding of 1 080p HD video of H.264/AVC (AVS) at the working frequency of 186MHz in Xilinx Virtex5 FPGA, and reduce 33% area cost when compared with two separate designs．
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Published: 01 May 2012
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基于FPGA的可重构视频编码器设计
针对现场可编程门阵列（FPGA）平台,提出可重构视频编码（RVC）的硬件实现方案.为提高系统吞吐量和功能单元（FU）的可重用及可扩性,提出分层的、多颗粒度并存的、可重用的功能单元设计方法；为重构的简单性及降低实现复杂度,提出在功能单元之间采用不同的存储结构作为数据连接方式.最终实现支持H.264/AVC和AVS的全I帧可重构视频编码器.结果表明,该编码器在Xilinx Virtex-5 330上能够分别实现H.264/AVC标准下25帧及AVS标准下37帧1 920×1 080视频的实时编码,比2个标准单独的设计实现代价降低了33%.
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