XIU Si-wen1, LI Yan-zhe1, HUANG Kai1, MA De2, YAN Rong-jie3, YAN Xiao-lang1
1. Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China; 2. Microelectronics CAD Center, Hangzhou Dianzi University, Hangzhou 310018, China;
3. Institute of Software, Chinese Academy of Sciences, Beijing 100080, China
The disadvantages of existing cache modeling techniques for MPSoC performance estimation were analyzed. An static analysis and dynamic annotation combined cache modeling technique for native simulation was proposed. The technique employs GCC profiling, avoids tag-search for hit/miss judgment, and coarsens the granularity of cache updating. An accurate address mapping table for instruction and all types of data variables was established, which improves both simulation speed and estimation accuracy. Multi-level cache modeling was considered, which extends support for multi-processor platform. Experimental results show that the proposed technique can significantly reduce the simulation time and improve the accuracy of estimation result compared with existing techniques．
XIU Si-wen, LI Yan-zhe, HUANG Kai, MA De, YAN Rong-jie, YAN Xiao-lang. Cache modeling for MPSoC performance estimation. JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), 2015, 49(7): 1367-1375.
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