[1] DUVVURY C. ESD protection device issues for IC designs[C]//2001 IEEE Custom Integrated Circuits. San Diego,USA:IEEE, 2001:41-48.
[2] KER M D, HSU K C. Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits[J]. IEEE Transactions on Device and Materials Reliability, 2005, 5(2):235-249.
[3] SALCEDO J A, LIOU J J, BERBIER J C. Design and integration of novel SCR-based devices for ESD protection in CMOS/BiCMOS technologies[J]. IEEE Transactions on Electron Devices, 2005, 52(12):2682-2689.
[4] 李冰,王刚,杨袁渊.基于SCR的ESD保护电路防闩锁设计[J].微电子学,2009,39(6):786-789. LI Bing, WANG Gang, YANG Yuan-yuan. Latch-up free design of SCR-based ESD protection circuits[J]. Microelectronics, 2009, 39(6):786-789.
[5] LIU Z W, VINSON J, LOU L F, et al. An improved bidirectional SCR structure for low-triggering ESD protection applications[J]. IEEE Electron Device Letters, 2008, 29(4):360-362.
[6] WANG Y, JIN X L, YANG L, et al. Robust dual-direction SCR with low trigger voltage, tunable holding voltage for high-voltage ESD protection[J]. Microelectronics Reliability, 2015, 55(3):520-526.
[7] VASHCHENKO V A, HOPPER P J. New dual-direction ESD device in Si-Ge BiCMOS process[C]//2010 IEEE 10th International Conference on Solid-State and Integrated Circuit Technology. Shanghai:IEEE, 2010:935-937.
[8] 梁海莲,董树荣,顾晓峰,等.基于0.5μm BCD工艺的双向SCR结构的ESD保护设计[J].浙江大学学报:工学版,2013, 47(11):2046-2050. LIANG Hai-lian, DONG Shu-rong, GU Xiao-feng, et al. ESD protection design of DDSCR structure based on the 0.5μm BCD process[J]. Journal of Zhejiang University:Engineering Science, 2013, 47(11):2046-2050.
[9] GUO W, LI M L, DONG S R. Effect of metal routing on the ESD robustness of dual-direction silicon controlled rectifier[C]//2009 IEEE 16th International Symposium on the Physical and Failure Analysis of Integrated Circuits. Suzhou:IEEE, 2009:336-338.
[10] DU X Y, DONG S R, HAN Y, et al. Analysis of metal routing technique in a novel dual direction multi-finger SCR ESD protection device[C]//2008 IEEE 9th International Conference on Solid-State and Integrated Circuit Technology. Beijing:IEEE, 2008:337-340.
[11] LEE J C, YOUNG R, LIOU J J, et al. An improved transmission line pulsing (TLP) setup for electrostatic discharge (ESD) testing in semiconductor devices and ICs[C]//2001 IEEE International Conference on Microelectronic Test Structures. Kobe:IEEE, 2001:233-238.
[12] WANG Y, LU G Y, ZHANG L Z, et al. Comprehensive study and corresponding improvements on the ESD robustness of different nLDMOS devices[C]//2014 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits. Marina Bay Sands, Singapore:IEEE, 2014:304-307. |