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浙江大学学报(工学版)
JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE)
Information Engineering     
Design of chip-level clock system using frequency tunable standing-wave oscillators
ZHANG Wei, HU You de, ZHENG Li rong
School of Information Science and Technology, Fudan University, Shanghai 200433, China
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Abstract  

A new frequency tunable standing-wave oscillator architecture using inversion mode MOSFET（IMOS）as varactors was introduced. The frequency tuning range and power of oscillator were simulated when varactors were placed in lumped mode and distributed mode. In 65 nm technology, the simulation results showed that lumped mode had wider tuning range than the distributed mode with a little more power dissipation, and the tuning range achieved 20%. New chip-level clock systems were designed for global synchronous chip and global asynchronous local synchronous chip using frequency tunable standing-wave oscillator with lumped varactors. Simulation results of different process voltage temperature (PVT) settings show that these clock systems can distribute high frequency clock signal with high reliability.

Published: 01 January 2017
CLC:  TN 402  
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ZHANG Wei, HU You de, ZHENG Li rong. Design of chip-level clock system using frequency tunable standing-wave oscillators. JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), 2017, 51(1): 168-176.


基于频率可调驻波振荡器的芯片时钟系统设计

介绍采用基于反型金属氧化物半导体场效应晶体管（IMOS）的变容二极管（varactor）实现频率可调节驻波振荡器的设计结构,通过仿真对比驻波振荡器中可变电容集总式分布和离散式分布对频率调节范围和功耗的影响.在65 nm工艺下的仿真结果表明,集总式分布的可变电容可以使驻波振荡器以较小的功耗增长获得更大的频率调节范围,频率调节范围可以达到20%.基于该振荡器提出全局同步芯片、全局异步局部同步芯片中时钟系统设计结构,通过仿真测试这些时钟系统在不同温度波动、电压波动和工艺偏差下的频率变化.仿真结果表明,这些结构可以实现高频时钟在指定芯片区域内的高可靠、可调节传输.

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