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浙江大学学报(工学版)
浙江大学学报(工学版)  2023, Vol. 57 Issue (9): 1894-1902    DOI: 10.3785/j.issn.1008-973X.2023.09.021
电子、通信与自动控制技术     
H.266/VVC二维变换的统一硬件结构
陈俊煜1(),孙斌1,*(),黄晓峰2,盛庆华3,赖昌材3,金心宇1
1. 浙江大学 工程师学院，浙江 杭州 310015
2. 杭州电子科技大学 通信工程学院，浙江 杭州 310018
3. 杭州电子科技大学 电子信息学院，浙江 杭州 310018
Unified hardware architecture for 2D transform in H.266/VVC
Jun-yu CHEN1(),Bin SUN1,*(),Xiao-feng HUANG2,Qing-hua SHENG3,Chang-cai LAI3,Xin-yu JIN1
1. Polytechnic Institute, Zhejiang University, Hangzhou 310015, China
2. School of Communication Engineering, Hangzhou Dianzi University, Hangzhou 310018, China
3. School of Electronics and Information, Hangzhou Dianzi University, Hangzhou 310018, China
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摘要：

为了降低H.266/VVC中二维变换部分的硬件实现面积和功耗，提出统一的硬件结构，支持全尺寸的离散余弦变换(DCT-II, DCT-VIII)和离散正弦变换(DST-VII). 所提结构包括2个并行的一维变换模块和1个转置存储器，其中一维变换模块基于多常量乘法(MCM)设计，针对所有的变换类型和尺寸设计可复用的MCM计算单元. 为了能够支持混合块的流水输入，设计支持流水线处理的转置存储器. 该转置存储器基于静态随机存储器(SRAM)实现，使用对角线存储方案并配合读写指针进行操作，利用先入先出队列(FIFO)进行块信息缓存. 实验结果表明，统一的计算单元可以减小变换结构1.3%的面积和49.5%的功耗，转置存储器能够结合VVC高频置零的特性减少SRAM一半的存储空间.
关键词： H.266/VVC;  离散余弦变换(DCT);  离散正弦变换(DST);  硬件结构;  专用集成电路(ASIC);  流水线    
Abstract:

A unified hardware architecture was proposed in order to reduce the hardware implementation area and the power of the 2D transform in H.266/VVC. The architecture supported the full-size discrete cosine transform (DCT-II, DCT-VIII) and the discrete sine transform (DST-VII). The architecture consisted of two parallel 1D transform modules and one transpose memory. The 1D transform module was designed based on the multiple constant multiplication (MCM), and a reusable MCM computing unit was designed for all transform types and sizes. The transpose memory was proposed in order to support the pipeline input of the mixed blocks. And the transpose memory was implemented based on static random-access memory (SRAM), used a diagonal storage method with read and write pointers, and used first input first output (FIFO) to cache block information. Experimental results showed that the unified computing unit reduced the area of the transform architecture by 1.3% and the power consumption by 49.5%, and the transpose memory reduced the SRAM storage space by half with the high-frequency zeroing feature of VVC.
Key words: H.266/VVC    discrete cosine transform (DCT)    discrete sine transform (DST)    hardware architecture    application-specific integrated circuit (ASIC)    pipeline
收稿日期: 2022-11-21 出版日期: 2023-10-16
CLC:  TN 919.81  
基金资助: 国家自然科学基金资助项目(61901150)；浙江省科技计划资助项目(LGG18F010004)；科技部-科技创新2030重大项目(2021ZD0109802)
通讯作者: 孙斌     E-mail: chenjunyu@zju.edu.cn;shg@zju.edu.cn
作者简介: 陈俊煜（1999—），男，硕士生，从事移动智慧物联网研究. orcid.org/0000-0002-2206-5564. E-mail： chenjunyu@zju.edu.cn
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引用本文:

陈俊煜,孙斌,黄晓峰,盛庆华,赖昌材,金心宇. H.266/VVC二维变换的统一硬件结构[J]. 浙江大学学报(工学版), 2023, 57(9): 1894-1902.

Jun-yu CHEN,Bin SUN,Xiao-feng HUANG,Qing-hua SHENG,Chang-cai LAI,Xin-yu JIN. Unified hardware architecture for 2D transform in H.266/VVC. Journal of ZheJiang University (Engineering Science), 2023, 57(9): 1894-1902.

链接本文:

https://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2023.09.021    或    https://www.zjujournals.com/eng/CN/Y2023/V57/I9/1894

图 1  二维变换的流水线结构
图 2  DCT-II的2种变换矩阵
图 3  DST-VII4与DCT-VIII4的变换关系
图 4  基于MCM的一维变换统一结构
图 5  蝶形运算结构
图 6  DST-VII和DCT-VIII的统一结构
图 7  不同输入数据对应的移位加法单元
图 8  转置存储器结构
图 9  输入矩阵与存储结构
图 10  二维变换流水线结构时序图
方法 标准 工艺 F/MHz H/(像素·周期?1) NGC/103 P/mW N 变换类型
DCT-II DST-VII DCT-VIII
文献[10] VVC 65 nm 250 32 496.4 62.6 4~32 × √ √
文献[13] VVC 28 nm 600 1 89.1 — 4~64 √ √ √
文献[14] VVC 90 nm 160 8 416.0 — 4~32 √ √ √
文献[17] HEVC 90 nm 187 32 347.0 67.6 4~32 √ × ×
文献[21] HEVC 90 nm 300 8,8,4,2 166.0 23.2 4~32 √ × ×
本研究 VVC 28 nm 724 32 1 121.5 48.2 4~64 √ √ √
表 1  基于ASIC实现的二维变换硬件设计对比
方法 标准 H/(像素·周期?1) NB D W N 变换类型
DCT-II DST-VII DCT-VIII
文献[8] VVC 4 16 512 16 4~32 √ √ √
文献[10] VVC 32 32 64 16 4~32 × √ √
本研究 VVC 32 32 128 16 4~64 √ √ √
表 2  转置存储器硬件设计对比
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