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J4  2011, Vol. 45 Issue (4): 656-659    DOI: 10.3785/j.issn.1008-973X.2011.04.011
曹晓阳1, 潘赟1, 严晓浪1, 宦若虹2
1.浙江大学 超大规模集成电路设计研究所,浙江 杭州 310027; 2.浙江工业大学 计算机科学与技术学院,浙江 杭州 310023
Systolic structure for DCT with low area-time complexity
CAO Xiao-yang1, PAN Yun1, YAN Xiao-lang1, HUAN Ruo-hong2
1. Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China; 2. College of Computer Science
and Technology, Zhejiang University of Technology, Hangzhou 310023, China
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为了研究脉动结构在离散余弦变换(DCT)算法中的应用以及平衡DCT算法在超大规模集成电路(VLSI)实现中对面积复杂度和时间复杂度的要求,提出一种基于脉动阵列的DCT结构.研究一维DCT变换的特点,对DCT进行公式变形.充分挖掘DCT算法中可以重复利用的数据,从而减少运算量.针对变形后的算法特点,采用脉动结构进行求解,从而提高并行度,减少运算时间.结果表明,相对于现有的脉动结构,该结构具有更小的面积-时间复杂度(area-time complexity),对DCT长度的限制小,仅要求DCT变换的长度为偶数.


A systolic-array based discrete cosine transform (DCT) was proposed in order to study the application of systolic array in DCT and balance the area complexity and time complexity in the very large scale integrated-circuit (VLSI) implementation of DCT. The characteristic of DCT was analyzed and the one-dimensional DCT formula was transformed. The data items that can be reused were found to reduce computation. The systolic structure which can save computing time by higher parallelism was used to solve the deformed DCT algorithm. Results show that the structure has lower areatime complexity than the previous systolic-array based structures, and has a smaller restriction on the length of DCT, only requiring an even number.

出版日期: 2011-05-05
:  TP 302  


通讯作者: 潘赟,男,副教授.     E-mail:
作者简介: 曹晓阳(1987—),男,河南孟州人,硕士生,从事集成电路设计及研究
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曹晓阳, 潘赟, 严晓浪, 宦若虹. 低面积-时间复杂度的离散余弦变换脉动结构[J]. J4, 2011, 45(4): 656-659.

CAO Xiao-yang, PAN Yun, YAN Xiao-lang, HUAN Ruo-hong. Systolic structure for DCT with low area-time complexity. J4, 2011, 45(4): 656-659.


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