Please wait a minute...
浙江大学学报(工学版)
J4  2010, Vol. 44 Issue (2): 300-304    DOI: 10.3785/j.issn.1008-973X.2010.02.016
计算机技术﹑电信技术     
双电压动态可重构FPGA任务模型及调度算法
徐科君, 许文曜, 沈继忠, 徐新民
（浙江大学 电子电路与信息系统研究所,浙江 杭州 310027）
Task scheduling model and algorithm based on dual-Vdd dynamic reconfigurable FPGA
XU Ke-jun, XU Wen-yao, SHEN Ji-zhong, XU Xin-min
(Institute of Electronic Circuit and Information System,Zhejiang University,Hangzhou 310027,China)
 全文: PDF  HTML
摘要：

通过对单电压动态可重构可编程逻辑门阵列（FPGA）实时任务模型的学习研究,建立基于双电压动态可重构FPGA的非可抢占任务模型.该模型很好地描述了双电压动态可重构FPGA任务的特征,在单电压任务模型的基础上增加了双电压任务模型特有的属性.并基于降序首次自适应算法提出一种新的硬件任务调度算法,该算法在保证任务集限制时间内完成所有任务的同时,利用动态电压调节的方法大幅度减少了任务集完成所需要的能量.在Sun Saloris 工作站下对任务调度模型及其算法进行仿真和评估,实验数据表明,这种基于双电压的任务模型的调度算法,能够有效降低FPGA任务执行的能耗，对于大规模的任务,能耗最高可节省24.1%.
Abstract:

A non-preemptive task model based on dual-supply voltage (Vdd) dynamic reconfigurable field programmable gate array (FPGA) was established by analyzing single voltage reconfigurable FPGA. The model described how the tasks excused in dual-Vdd dynamic reconfigurable FPGA and added special attributes of dual-Vdd task model based on single voltage task model. A novel scheduling strategy was proposed based on the first-fit-decreasing algorithm. The strategy can guarantee the execution deadline of the task set and greatly reduce the execution energy using dynamic adjustment of dual-Vdd. The experiment simulated on Sun Saloris shows that the strategy can achieve the great energy saving, which is up to 24.1% of large task set.
出版日期: 2010-03-09
:  TN 432  
基金资助:

国家自然科学基金资助项目（90207002）.
通讯作者: 沈继忠，男，教授，博导.     E-mail: jzshen@zju.edu.cn
作者简介: 徐科君(1983—)，男，浙江杭州人，博士生,从事FPGA结构体系、任务调度、低功耗等研究.
服务　　
把本文推荐给朋友
加入引用管理器
E-mail Alert
RSS
作者相关文章　　

引用本文:

徐科君, 许文曜, 沈继忠, 等. 双电压动态可重构FPGA任务模型及调度算法[J]. J4, 2010, 44(2): 300-304.

XU Ke-Jun, HU Wen-Yao, CHEN Ji-Zhong, et al. Task scheduling model and algorithm based on dual-Vdd dynamic reconfigurable FPGA. J4, 2010, 44(2): 300-304.

链接本文:

http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2010.02.016    或    http://www.zjujournals.com/eng/CN/Y2010/V44/I2/300

［1］  GUPTA R K. FPGA-enabled computing architectures ［J］. IEEE Design and Test of Computers, 2005, 22(2): 81.
［2］ Xilinx Company. User guides and technologic reports ［EB/OL］. ［2005-08-15］. http://www.xilinx.com/.
［3］ 覃祥菊,朱明程,张太镒,等.FPGA动态可重构技术原理及实现方法分析［J］.电子器件,2004, 27(2): 277282.
TAN Xiang-ju, ZHU Ming-cheng, ZHANG Tai-yi, et al. Analysis of the fundamental and implementation method about dynamic reconfigurable FPGA ［J］. Chinese Journal of Electron Devices, 2004, 27(2): 277282.
［4］ WANG F, JEAN J S N. Architectural support for runtime 2D partial reconfiguration［C］// International Conferen- ce on Engineering of Reconfigurable Systems and Algorithms. Las Vegas: CSREA, 2006： 231236.
［5］ CHOW C T, TSUI L S M, LEONG P H W, et al. Dynamic voltage scaling for commercial FPGAs ［C］// Proceedings of the IEEE International Conference on Field-Programmable Technology. Kyoto, Japan: IEEE, 2005： 173180.
［6］ BOWER J A, LUK W, MENCER O, et al. Dynamic clock-frequencies for FPGAs［J］. Microprocessors and Microsystems, 2006, 6(30): 388397.
［7］ GAYASEN A, LEE K, NARATANAN V, et al. A dual-VDD low power FPGA architecture ［C］// Intern- ational Conference on Field Programmable Logic and Applications. Leuven: Computer Science, 2004: 5158.
［8］ LIN Yan, LI Fei, HE Lei. Circuits and architectures for field programmable gate array with configurable supply voltage［J］. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005, 13(9): 10351047.
［9］ 徐新民,吴晓波,严晓浪.现场可编程门阵列动态重构下的低功耗研究［J］.浙江大学学报:工学版,2007, 41(2): 193197.
XU Xin-min, WU Xiao-bo, YAN Xiao-lang. Research on low power consumption of field-programmable gate arrays in run-time reconfiguration［J］. Journal of Zhejiang University： Engineering Science, 2007, 41(2): 193197.
［10］ GU Zong-hua, YUAN Ming-xuan, HE Xiu-qiang. Real-time task scheduling analysis on partially runtime reconfigurable FPGAs using model-checking ［C］// IEEE Real-Time and Embedded Technology and Applications Symposium. Bellevue: IEEE, 2007: 3244.
［11］ BURD T, BRODERSON R. Design issues for dynamic voltage scaling［C］ //Proceedings of the International Symposium on Low Power Electronics and Design. Rapallo, Italy: IEEE, 2000: 914.
［12］ TUAN T, TRIMBERGER S. The power of FPGA architectures ［R］. San Jose, California: Xilinx company, 2007.
［13］ WANG H, DELAHAYE J, LERAY P, et al. Managing dynamic reconfiguration on MIMO decoder\
[C\]//The 14th Reconfigurable Architectures Workshop. Long Beach California, USA:\
[s.n.\], 2007: 2630.
［14］ COFFMAN J, GARAY M, JOHNSON D. Approximation algorithms for bin packing problems: a survey ［C］ // Computational Complexity Analysis and Design of Algorithms for Combinatorial Optimization Prob- lems. New York: Springer-Verlag, 1981: 147172.
［15］ 倪刚,童家榕,来金梅.基于对可编程逻辑块建模的FPGA通用装箱算法［J］.计算机工程,2007, 33(6): 239244.
NI Gang, TONG Jia-rong, LAI Jin-mei. Universal packing algorithm for FPGA based on logic block modeling ［J］. Computer Engineering. 2007, 33(6): 239244.
［16］ LIU Yong-pan,YANG Hua-zhong,DICK R P. Thermal vs energy optimization for DVFS-enabled processors in embedded systems ［C］ // Proceedings of the 8th International Symposium on Quality Electronic Design. Hang Zhou: IEEE, 2007.
[1] 雷鑑铭, 胡北稳, 桂涵姝, 张乐. 采用新型低成本共模反馈电路的全差分运放设计[J]. J4, 2013, 47(10): 1777-1783.
[2] 杭国强, 李锦煊, 王国飞. 新型钟控神经元MOS采样/保持电路[J]. J4, 2012, 46(2): 333-337.
[3] 韩雁 , 廖璐 , 黄小伟 , 张昊 , 王昊. 多比特量化的音频DAC中模拟电路的设计[J]. J4, 2011, 45(9): 1571-1575.
[4] 肖林荣, 陈偕雄, 应时彦. 基于模块化技术的最佳ULG.2的QCA电路设计[J]. J4, 2011, 45(6): 1032-1037.
[5] 徐扬, 沈继忠. 基于门控时钟的低功耗时序电路设计新方法[J]. J4, 2010, 44(9): 1724-1729.
[6] 杭国强, 应时彦. 新型电流型CMOS四值边沿触发器设计[J]. J4, 2009, 43(11): 1970-1974.
[7] 章丹艳, 吴晓波, 赵梦恋, 等. 光伏电池最大功率点跟踪芯片的设计[J]. J4, 2009, 43(11): 2000-2005.