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浙江大学学报(工学版)  2019, Vol. 53 Issue (12): 2423-2430    DOI: 10.3785/j.issn.1008-973X.2019.12.021
采用0.18 μm CMOS工艺的高速模拟自适应判决反馈均衡器
东南大学 射频与光电集成电路研究所,江苏 南京 210096
High-speed analog-adaptive decision feedback equalizer with 0.18 μm CMOS technology
Yong-zheng ZHAN(),Qing-sheng HU*()
Institute of RF- and OE-ICs, Southeast University, Nanjing 210096, China
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采用0.18 μm CMOS工艺设计实现适用于高速背板通信的2抽头模拟自适应判决反馈均衡器(DFE). 采用半速率结构提高电路工作速度, 降低功耗, 并设计由乘法器和积分器构成的模拟最小均方(LMS)自适应电路. 为了改善自适应算法的效果, 对模拟LMS电路进行优化设计, 使其既满足自适应算法的收敛性和稳定性要求, 又能获得较小的积分误差, 并且积分器能够输出稳定的偏置电压. 包括整个焊盘在内的芯片面积为0.378 mm2. 测试结果表明:电路自适应开启时能够对4 GHz损耗为12 dB的信道进行有效补偿, 且垂直张开度和水平张开度分别达到275.5 mV和72 ps, 均衡效果明显优于自适应关闭状态. 当电源电压为1.8 V、工作速度为8 Gb/s时,电路的功耗为49.9 mW. 所设计的模拟自适应DFE电路更适用于25 G及以上的高速通信链路系统.

关键词: 判决反馈均衡器(DFE)半速率最小均方(LMS)积分器    

A 2-tap analog-adaptive decision feedback equalizer (DFE) was designed using 0.18 μm CMOS technology for high-speed backplane communication. Half-rate architecture was adopted to improve the speed and reduce the power. And analog least-mean-square adaptive circuit composed of multiplier and integrator was designed. In order to improve the effect of adaptive algorithm, LMS analog circuit was optimized, which not only ensured the requirement of the adaptive convergence and stability, but also obtained the smaller integral error to output the stable bias voltage for integrator. The whole chip area including pads was 0.378 mm2. The test results show that DFE can compensate 12 dB channel loss at 4 GHz when adaptive circuit was turned on, and the vertical opening and horizontal opening reached 275.5 mV and 72 ps, respectively, which was significantly better than that when it was turned off. The power consumption was 49.9 mW at the supply voltage of 1.8 V and the rate of 8 Gb/s. The designed analog-adaptive DFE circuit is more suitable for high-speed communication link systems of 25 G and above.

Key words: decision feedback equalizer (DFE)    half-rate    least-mean-square (LMS)    integrator
收稿日期: 2018-11-06 出版日期: 2019-12-17
CLC:  TN 432  
基金资助: 国家自然科学基金资助项目 (61471119)
通讯作者: 胡庆生     E-mail:;
作者简介: 展永政(1989—),男,博士生,从事高速集成电路设计. 0000-0002-1885-5950. E-mail:
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展永政,胡庆生. 采用0.18 μm CMOS工艺的高速模拟自适应判决反馈均衡器[J]. 浙江大学学报(工学版), 2019, 53(12): 2423-2430.

Yong-zheng ZHAN,Qing-sheng HU. High-speed analog-adaptive decision feedback equalizer with 0.18 μm CMOS technology. Journal of ZheJiang University (Engineering Science), 2019, 53(12): 2423-2430.


图 1  符号-符号最小均方(S-S LMS)算法实现框图
图 2  模拟最小均方(LMS)电路实现框图
图 3  模拟自适应半速率判决反馈均衡器(DFE)
图 4  D 触发器 (DFF)原理图
图 5  加乘器原理图
图 6  Gilbert乘法器原理图
图 7  积分器电路原理图
图 8  所设计的乘法器的频率响应
图 9  不同积分时间常数下LMS算法的收敛特性
图 10  自适应均衡效果的仿真结果
图 11  芯片显微照片
图 12  芯片测试方案及仪器
图 13  8 Gb/s 2抽头模拟自适应DFE测试结果
来源 CMOS工艺 v/(Gb·s-1) 结构 DFE自适应 S/mm2 P/mW L/dB U/V
注:1)包含时钟及数据恢复(clock and data recovery, CDR)的功耗
本文 0.18 μm 8.00 半速率DFE 模拟 0.378 49.9 12.0 1.8
文献[14] 0.18 μm 6.25 半速率DFE 数字 0.33 49.5 9.7 1.8
文献[15] 40 nm 15.00 CTLE+半速率预处理DFE 模拟 2.03 72.5 23.0 1.1
文献[16] 0.13 μm 10.00 FFE+全速率DFE 模拟 5.52 452.01) 16.3 1.2
表 1  不同自适应均衡器的性能比较
1 NEHA S, MOHIT P. Channel equalization using linear and decision feedback equalizers [C] // International Conference on Computing, Communication and Networking Technologies (ICCCNT), Delhi: ICCCNT, 2017: 1-5.
2 THOMAS T, MATTHIAS B, ALESSANDRO C, et al. Design considerations for 50 G+ backplane links [C] // European Solid-State Circuits Conference (ESSCIRC). Lausanne: ESSCIRC, 2016: 477-482.
3 PARAG U, CHI F P, SIOK W L, et al A fully adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ wireline transceiver with configurable ADC in 16-nm FinFET[J]. IEEE Journal of Solid-State Circuits, 2019, 54 (1): 18- 28
doi: 10.1109/JSSC.2018.2875091
4 BROWN J E C, HURST P J, DER L A 35 Mb/s mixed-signal decision-feedback equalizer for disk drives in 2-μm CMOS[J]. IEEE Journal of Solid-State Circuits, 1996, 31 (9): 1258- 1266
doi: 10.1109/4.535409
5 BEUKEMA T, SORNA M, SELANDER K, et al A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization[J]. IEEE Journal of Solid-State Circuits, 2005, 40 (12): 2633- 2645
doi: 10.1109/JSSC.2005.856584
6 EMAMI-NEYESTANAK A, VARZAGHANI A, BULZACCHELLI J F, et al A 6.0-mW 10.0-Gb/s receiver with switched-capacitor summation DFE[J]. IEEE Journal of Solid-State Circuits, 2007, 42 (4): 889- 896
doi: 10.1109/JSSC.2007.892156
7 MILIJEVIC S, KWASNIEWSKI T 4 Gbit/s receiver with adaptive blind DFE[J]. Electronics Letters, 2005, 41 (25): 1373- 1374
doi: 10.1049/el:20053165
8 MVSR T, MEGHASHYAM K, VERMA A. Comprehensive analysis of LMS and NLMS algorithms using adaptive equalizers [C] // International Conference on Communication and Signal Processing (ICCSP). Melmaruvathur: ICCSP, 2014: 1101-1104.
9 ZHANG T B, HU Q S. A high-speed and low-power up/down counter in 0.18 μm CMOS Technology [C] // International Conference on Wireless Communications and Signal Processing (WCSP). Huangshan: WCSP, 2013: 1-3.
10 KARGAR M, GREEN M M. A 10 Gb/s adaptive analog decision feedback equalizer for multimode fiber dispersion compensation in 0.13μm CMOS [C] // European Conference Solid-State Circuits (ESSCIRC). Seville: ESSCIRC, 2010: 550-553.
11 PATEL P. Realization of logic gates using CMOS Gilbert multiplier cell [C] // IEEE International Advance Computing Conference (IACC). Ghaziabad: IACC, 2013: 1577-1581.
12 MULLER N, MANOLI Y, KUHL M. A 1.6nS, 16μW, 30V Gm-C integrator for offset voltage monitoring in neural stimulators [C] // IEEE International Symposium on Circuits and Systems (ISCAS). Melbourne VIC: ISCAS, 2014: 2381-2384.
13 ROSHAN-ZAMIR A, IWAI T, FAN Y H, et al A 56-Gb/s PAM4 receiver with low-overhead techniques for threshold and edge-based DFE FIR- and IIR-tap adaptation in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2019, 54 (3): 672- 684
doi: 10.1109/JSSC.2018.2881278
14 WU X, HU Q S. Design of a 6.25 Gb/s adaptive decision feedback equalizer in 0.18 μm CMOS technology [C] // IEEE Workshop on Advanced Research and Technology in Industry Applications (WARTIA). Ottawa: WARTIA, 2014: 1209-1212.
15 VAMVAKOS S D, BOECKER C, GROEN E, et al. A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop [C] // Custom Integrated Circuits Conference (CICC). San Jose: CICC, 2014: 1-4.
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