| 电子工程、电气工程 |
|
|
|
|
| 新型VBO接口芯片静电放电防护器件 |
徐泽坤( ),沈宏宇,胡涛,李响,董树荣*() |
| 浙江大学 微电子学院ESD实验室，浙江 杭州 310027 |
|
| New electrostatic discharge protection device for VBO high speed chip |
| Ze-kun XU(),Hong-yu SHEN,Tao HU,Xiang LI,Shu-rong DONG*() |
| School of Microelectronics ESD Laboratory, Zhejiang University, Hangzhou 310027, China |
引用本文:
徐泽坤,沈宏宇,胡涛,李响,董树荣. 新型VBO接口芯片静电放电防护器件[J]. 浙江大学学报(工学版), 2019, 53(4): 794-800.
Ze-kun XU,Hong-yu SHEN,Tao HU,Xiang LI,Shu-rong DONG. New electrostatic discharge protection device for VBO high speed chip. Journal of ZheJiang University (Engineering Science), 2019, 53(4): 794-800.
链接本文:
http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2019.04.021
或
http://www.zjujournals.com/eng/CN/Y2019/V53/I4/794
|
| 1 |
MERRILL R, ISSAQ E. ESD design methodology [C] // Electrical Overstress/ Electrostatic Discharge Symposium. Lake Vista: IEEE, 1993: 233–237.
|
| 2 |
ABHHNAV V, CHATTERJEE A, SINHA D K, et al. Methodology for optimizing ESD protection for high speed LVDS based I/Os [C] // International Symposium on VlSI Design and Test. Hsinchu: IEEE, 2015: 1–5.
|
| 3 |
LIN C Y, KER M D, CHANG P H, et al. Study on the ESD-induced gate-oxide breakdown and the protection solution in 28 nm high-k metal-gate CMOS technology [C] // Nanotechnology Materials and Devices Conference. Toulouse: IEEE, 2016: 1–4.
|
| 4 |
曾杰. 新型集成电路ESD防护器件研究[D]. 浙江: 浙江大学, 2016.
ZENG Jie. Research of ESD protection device in new integrated circuit [D]. Zhejiang: Zhejiang University, 2016.
|
| 5 |
CHEN V, SALMAN A, BEEBE S, et al. SOI poly-defined diode for ESD protection in high speed I/Os [C] // Proceedings of IEEE International Reliability Physics Symposium. Piscataway: IEEE, 2006: 635–636.
|
| 6 |
LIN C Y, WU P H, KER M D Area-efficient and low-leakage diode string for on-chip ESD protection[J]. IEEE Transactions on Electron Devices, 2016, 63 (2): 531- 536
doi: 10.1109/TED.2015.2504493
|
| 7 |
LI C, WANG C, CHEN Q, et al. Characterization and analysis of diode-string ESD protection in 28 nm CMOS by VFTLP [C] // International Symposium on the Physical and Failure Analysis of Integrated Circuits. Chengdu: IEEE, 2017: 1–4.
|
| 8 |
YEH C T, KER M D, LIANG Y C Optimization on layout style of ESD protection diode for radio-frequency front-end and high-speed I/O interface circuits[J]. IEEE Transactions on Device and Materials Reliability, 2010, 10 (2): 238- 246
doi: 10.1109/TDMR.2010.2043433
|
| 9 |
CHATTERJEE A, POLGREEN T A low-voltage triggering SCR for on-chip ESD protection at output and input pads[J]. IEEE Electron Device Letters, 1991, 12 (1): 21- 22
doi: 10.1109/55.75685
|
| 10 |
KER M D, HSU K C. Complementary substrate- triggered SCR devices for on-chip ESD protection circuits [C] // ASIC/SOC Conference. New York: IEEE, 2002: 229–233.
|
| 11 |
GUO J, LIU J Z, TIAN R, et al. Novel diode-triggered silicon-controlled rectifier (DTSCR) for high-temperature low-voltage electrostatic discharge (ESD) applications [C] // IEEE International Nanoelectronics Conference. Chengdu: IEEE, 2016: 1–2.
|
| 12 |
LIU J, QIAN L, TIAN R, et al Self-triggered stacked silicon-controlled rectifier structure (STSSCR) for on-chip electrostatic discharge (ESD) protection[J]. Microelectronics Reliability, 2017, 71 (4): 1- 5
|
| 13 |
喻钊. FPGA全芯片ESD防护设计和优化[D]. 成都: 电子科技大学, 2012.
YU Zhao. FPGA full-chip ESD protection design and optimization [D]. Chengdu: University of Electronic Science and Technology of China, 2012.
|
| 14 |
MA F, HAN Y, DONG S R, et al Improved low-voltage-triggered SCR structure for RF-ESD protection[J]. IEEE Electron Device Letters, 2013, 34 (8): 1050- 1052
doi: 10.1109/LED.2013.2265411
|
|
Viewed |
|
|
|
Full text
|
|
|
|
|
Abstract
|
|
|
|
|
Cited |
|
|
|
|
| |
Shared |
|
|
|
|
| |
Discussed |
|
|
|
|
