[1] DODD P E, MASSENGILL L W. Basic mechanisms and modeling of single-event upset in digital microelectronics [J]. IEEE Transactions on Nuclear Science, 2003, 50(3): 583-602.
[2] El-MALEH A H, DAUD K A K. Simulation-based method for synthesizing soft error tolerant combinational circuits [J]. IEEE Transactions on Reliability, 2015, 64(3): 935-948.
[3] TOURE G, HUBERT G, CASTELLANI-COULIEK, et al. Simulation of single and multi-node collection: Impact on SEU occurrence in nanometric SRAM cells [J]. IEEE Transactions on Nuclear Science, 2011, 58(3): 862-869.
[4] CALIN T, NICOLAIDIS M, VELAZCO R. Upset hardened memory design for submicron CMOS technology [J]. IEEE Transactions on Nuclear Science, 1996, 43(6): 2874-2878.
[5] JAHINUZZAMAN S, RENNIE D, SACHDEV M. A soft error tolerant 10T SRAM bit-cell with differential read capability [J]. IEEE Transactions on Nuclear Science, 2009, 56(3): 3768-3773.
[6] SHAH J S, NAIM D, SACHDEV M. A 32 kb macro with 8T soft error robust SRAM cell in 65-nm CMOS [J]. IEEE Transactions on Nuclear Science, 2015,62(3): 1367-1374.
[7] LI L X, LI Y Q, MA Y, et al. A novel asymmetrical SRAM cell tolerant to soft errors [C]//Canadian Conference on Electrical and Computer Engineering. Halifax: IEEE, 2015: 1403-1408.
[8] D'ALESSIO M, OTTAVI M, LOMBARDI F. Design of a nanometric CMOS memory cell for hardening to a single event with a multiple node upset [J]. IEEE Transactions on Device and Materials Reliability, 2014, 14(1): 127-132.
[9] 周恒,李磊.一种加固SRAM单元DDICE及外围电路设计[J].微电子学与计算机,2015, 32(5): 68-72. ZHOU Heng, LI Lei. A hardened SRAM cell-DDICE and peripheral circuits design [J]. Microelectronics and Computer, 2015, 32(5): 68-72.
[10] RAJAEI R, ASGARI B, TABANDEH M, et al. Design of robust SRAM cells against single-event multiple effects for nanometer technologies [J]. IEEE Transactions on Device and Materials Reliability, 2015, 15(3): 429-436.
[11] BANSAL A, RAO R, KIM J J, et al. Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability [J]. Microelectronics Reliability, 2009, 49(6): 642-649.
[12] YANG H I, CHUANG C T, HWANG W. Impacts of NBTI and PBTI on power-gated SRAM with high-k metal-gate devices [C]//IEEE International Symposium on Circuits and Systems. Taipei: IEEE, 2009: 377-380.
[13] WANG K, CHEN L, YANG J. An ultra-low power fault tolerant SRAM design in 90 nm CMOS Electrical and Computer Engineering [C]//Canadian Conference on Electrical and Computer Engineering. St. John's: IEEE, 2009: 1076-1079.
[14] CHANG L, MONTOYE R K., NAKAMURA Y, et al. An 8T SRAM for variability tolerance and low-voltage operation in high performance caches [J]. IEEE Journal of Solid-State Circuits, 2008, 43(4): 956-963.
[15] 沈婧,薛海卫.基于DICE结构的SRAM抗辐照加固设计[J].电子与封装,2016,16(3): 26-30. SHEN Jing, XUE Hai-wei. Design of radiation hardened SRAM based on DICE [J]. Electronics and Packaging, 2016, 16(3): 26-30.
[16] LEE Z C, HO K M, KONG Z H, et al. NBTI/PBTI-aware WWL voltage control for half-selected cell stability improvement [J]. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2013, 60(9): 602-606.
[17] RENNIE D, LI D, SACHDEV M, et al. Performance, metastability, and soft-error robustness trade-offs for flip-flops in 40 nm CMOS [J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2012, 59(8): 1626-1634.
[18] YANG H I, HWANG W, CHUANG C T. Impacts of NBTI/PBTI and contact resistance on power-gated SRAM with high-k metal-gate devices [J]. IEEE Transactions on Very Large Scale Integration Systems, 2011, 19(7): 1192-1204.
[19] YANG H I, YANG S C, HWANG W, et al. Impacts of NBTI/PBTI on timing control circuits and degradation tolerant design in nanoscale CMOS SRAM [J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2011, 58(6): 1239-1251.
[20] Predictive technology model [EB/OL]. [2011-06-01]. http://www.eas.asu.edu/~ptm.
[21] NAPHADE T, VERMA P, GOEL N, et al. DC/AC BTI variability of SRAM circuits simulated using a physics-based compact model [C]//IEEE International Reliability Physics Symposium. Waikoloa HI: IEEE, 2014: CA.2.1-CA.2.8.
[22] 李广林,张杰,商中夏,等.适应于动态电压频率调整的抗辐照SRAM设计[J].微电子学与计算机,2017,34(4): 33-38. LI Guang-lin, ZHANG Jie, SHANG Zhong-xia, et al. Microelectronics and Computer, 2017, 34(4): 33-38.
[23] 方海涛.高速低功耗嵌入式SRAM的设计[D].武汉:华中科技大学,2012. FANG Hai-tao. Design of high speed low power embedded SRAM. Wuhan: Huazhong University of Science and Technology, 2012. |