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浙江大学学报(工学版)  2017, Vol. 51 Issue (7): 1437-1445    DOI: 10.3785/j.issn.1008-973X.2017.07.023
信息工程     
用于容错片上网络的可工作性评估框架
蓝帆1, 潘赟2, 严晓浪2, 宦若虹3, CHENG Kwang-ting4
1. 浙江大学 电气工程学院, 浙江 杭州 310027;
2. 浙江大学 信息与电子工程学院, 浙江 杭州 310027;
3. 浙江工业大学 计算机科学与技术学院, 浙江 杭州 310023;
4. Electrical Computer Engineering, University of California, Santa Barbara, Santa Barbara 93106, USA
Workability evaluation framework for fault-tolerant network-on-chip
LAN Fan1, PAN Yun2, YAN Xiao-lang2, HUAN Ruo-hong3, CHENG Kwang-ting4
1. College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China;
2. College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China;
3. College of Computer Science and Technology, Zhejiang University of Technology, Hangzhou 310023, China;
4. Electrical Computer Engineering, University of California, Santa Barbara, Santa Barbara 93106, USA
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摘要:

针对片上网络良率分析过程忽略了诸如任务映射的结果与路由策略引入的通信约束等细节、不能准确地评估片上网络的实际工作情况的问题,提出“可工作性”概念和可工作性评估框架.该框架整合了良率、映射、路由3个模块和1个蒙特卡洛分析流程.通过仿真实验分析发现,不合适的映射算法与路由策略组合会使得可工作性比良率低80%以上;合适的映射算法与路由策略组合,能够保证可工作性与良率一致.使用这一框架,设计者能够评估片上网络芯片的可工作性,与良率评估相比,可工作性更接近片上网络的实际工作情况,因此更具有实际意义.

Abstract:

A new concept called workability was introduced and an evaluation framework for workability was proposed in order to address the issue that yield analysis ignores many details, such as task mapping results, and communication constraints induced by routing strategy, making yield analysis unable to accurately predict whether an NoC will work or not. The proposed framework integrated three components, i.e. yield, mapping, routing and one Monte Carlo analysis flow. The simulation analysis and results show that an improper combination of mapping algorithm and routing strategy will make workability 80% lower than yield, while a proper combination of mapping algorithm and routing strategy will make workability equal to yield. A designer can evaluate the workability of manufactured NoC chips with this framework. Since workability is more realistic than the yield, the evaluation framework will be meaningful.

收稿日期: 2016-03-01 出版日期: 2017-07-08
CLC:  TN47  
基金资助:

浙江省自然科学基金资助项目(LY15F020008);国家自然科学基金资助项目(61204030,61302129);浙江省科技厅公益性技术应用研究计划资助项目(2014C31045)

通讯作者: 潘赟,男,副教授.ORCID:0000-0002-9335-4291.     E-mail: panyun@vlsi.zju.edu.cn
作者简介: 蓝帆(1989—),男,博士生,从事片上网络的研究.ORCID:0000-0002-3299-9635.E-mail:lanfan@vlsi.zju.edu.cn
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引用本文:

蓝帆, 潘赟, 严晓浪, 宦若虹, CHENG Kwang-ting. 用于容错片上网络的可工作性评估框架[J]. 浙江大学学报(工学版), 2017, 51(7): 1437-1445.

LAN Fan, PAN Yun, YAN Xiao-lang, HUAN Ruo-hong, CHENG Kwang-ting. Workability evaluation framework for fault-tolerant network-on-chip. JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), 2017, 51(7): 1437-1445.

链接本文:

http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2017.07.023        http://www.zjujournals.com/eng/CN/Y2017/V51/I7/1437

[1] MARCULESCU R, OGRAS U Y, PEH L S, et al. Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2009, 28(1): 3-21.
[2] BELL S, EDWARDS B, AMANN J, et al. TILE64 processor: a 64-core SoC with mesh interconnect [C]//IEEE International Solid-State Circuits Conference-Digest of Technical Papers. San Francisco: IEEE, 2008: 88-89.
[3] VANGAL S, HOWARD J, RUHL G, et al. An 80-Tile 1.28TFLOPS network-on-chip in 65nm CMOS[C]//IEEE International Solid-State Circuits Conference-Digest of Technical Papers. San Francisco: IEEE, 2007: 98-99.
[4] KOREN I, KOREN Z. Defect tolerance in VLSI circuits: techniques and yield analysis [J]. Proceedings of the IEEE, 1998, 86(9): 1819-1838.
[5] KAHLE J A, DAY M N, HOFSTEE H P, et al. Introduction to the cell multiprocessor [J]. IBM Journal of Research and Development, 2005, 49(4.5): 589-604.
[6] PALESI M, KUMAR S, CATANIA V. Leveraging partially faulty links usage for enhancing yield and performance in Networks-on-Chip [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010, 29(3): 426-440.
[7] RODRIGO S, HERNANDEZ C, FLICH J, et al. Yield-oriented evaluation methodology of network-on-chip routing implementations [C]//International Symposium on System-on-Chip. Tampere: IEEE, 2009: 100-105.
[8] SHAMSHIRI S, CHENG K T. Modeling yield, cost, and quality of a spare-enhanced multicore chip [J]. IEEE Transactions on Computer, 2011, 60(9): 1246-1259.
[9] SHAMSHIRI S, CHENG K T. Yield and cost analysis of a reliable NoC [C]//IEEE VLSI Test Symposium. Washington: IEEE, 2009: 173-178.
[10] SHAMSHIRI S, CHENG K T. Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancy [C]//VLSI Test Symposium. Santa Cruz: IEEE, 2010: 194-199.
[11] LAN Fan, PAN Yun, CHENG K T. An efficient network-on-chip yield estimation approach based on Gibbs sampling [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, 35(3): 447-457.
[12] KOLOGESKI A, CONCATTO C, MATOS D, et al. Combining fault tolerance and serialization effort to improve yield in 3D networks-on-chip [C]//International Conference on Electronics, Circuits, and Systems. Dubayy: IEEE, 2013: 125-128.
[13] KAHNG A B, LI B, PEH L S, et al. Orion 2.0: a fast and accurate NoC power and area model for early-stage design space exploration [C]//Design, Automation Test in Europe Conference Exhibition. France: IEEE, 2009: 423-428.
[14] CHENG Ai-lian, PAN Yun, YAN Xiao-lang, et al. A general communication performance evaluation model based on routing path decomposition [J]. Journal of Zhejiang University-Science C: Computers and Electronics, 2011, 12(7): 561-573.
[15] 于绩洋,刘鹏,华幸成,等.片上光电互连的多核系统仿真方法[J].浙江大学学报:工学版,2015, 49(11): 2214-2222. YU Ji-yang, LIU Peng, HUA Xing-cheng, et al. Simulation approach of nybrid optical-electrical on-chip interconnects for multicore systems [J]. Journal of Zhejiang University: Engineering Science, 2015, 49(11): 2214-2222.
[16] CHIU G M. The odd-even turn model for adaptive routing [J]. IEEE Transactions on Parallel and Distributed Systems, 2000, 11(7): 729-738.
[17] MEJIA A, FLICH J, DUATO J, et al. Segment-based routing: an efficient fault-tolerant routing algorithm for meshes and tori [C]//Parallel and Distributed Processing Symposium. Rhodes Island: IEEE, 2006: 10-15.
[18] FLICH J, MEJIA A, LOPEZ P, et al. Region-based routing: an efficient routing mechanism to tackle unreliable hardware in network on chips [C]//International Symposium on Networks-on-Chip. Princeton: IEEE, 2007: 183-194.
[19] 全励,程爱莲,潘赟,等.基于旁路通道的片上网络差别型服务实现方法[J].浙江大学学报:工学版,2013,47(6): 957-968. QUAN Li, CHENG Ai-lian, PAN Yun, et al. Bypassed channels based differentiated service implementation method for network-on-chip [J]. Journal of Zhejiang University: Engineering Science, 2013, 47(6): 957-968.
[20] HU J, MARCULESCU R. Energy-and performance-aware mapping for regular NoC architectures [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005, 24(4): 551-562.
[21] KHOROUSH S, RESHADI M. A fault tolerant approach for application-specific network-on-chip [C]//NORCHIP. Lithuania: IEEE, 2013: 1-6.
[22] CONG J, LIU C, REINMAN G. Aces: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip [C]//Design Automation Conference (DAC). Anaheim: IEEE, 2010: 443-448.
[23] PALESI M, HOLSMARK R, KUMAR S, et al. Application specific routing algorithms for networks on chip [J]. IEEE Transactions on Parallel and Distributed Systems, 2009, 20(3): 316-330.
[24] ROBERT C, GEORGE C. Monte Carlo statistical methods [M]. 2nd ed. New York: Springer, 2004: 325-330.
[25] SHAO J. Mathematical statistics [M]. 2nd ed. New York: Springer, 2003: 524-530.

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