Please wait a minute...
浙江大学学报(工学版)
信息工程     
基于频率可调驻波振荡器的芯片时钟系统设计
张伟, 胡友德, 郑立荣
复旦大学 信息科学与工程学院,上海 200433
Design of chip-level clock system using frequency tunable standing-wave oscillators
ZHANG Wei, HU You de, ZHENG Li rong
School of Information Science and Technology, Fudan University, Shanghai 200433, China
 全文: PDF(1818 KB)   HTML
摘要:

介绍采用基于反型金属氧化物半导体场效应晶体管(IMOS)的变容二极管(varactor)实现频率可调节驻波振荡器的设计结构,通过仿真对比驻波振荡器中可变电容集总式分布和离散式分布对频率调节范围和功耗的影响.在65 nm工艺下的仿真结果表明,集总式分布的可变电容可以使驻波振荡器以较小的功耗增长获得更大的频率调节范围,频率调节范围可以达到20%.基于该振荡器提出全局同步芯片、全局异步局部同步芯片中时钟系统设计结构,通过仿真测试这些时钟系统在不同温度波动、电压波动和工艺偏差下的频率变化.仿真结果表明,这些结构可以实现高频时钟在指定芯片区域内的高可靠、可调节传输.

Abstract:

A new frequency tunable standing-wave oscillator architecture using inversion mode MOSFET(IMOS)as varactors was introduced. The frequency tuning range and power of oscillator were simulated when varactors were placed in lumped mode and distributed mode. In 65 nm technology, the simulation results showed that lumped mode had wider tuning range than the distributed mode with a little more power dissipation, and the tuning range achieved 20%. New chip-level clock systems were designed for global synchronous chip and global asynchronous local synchronous chip using frequency tunable standing-wave oscillator with lumped varactors. Simulation results of different process voltage temperature (PVT) settings show that these clock systems can distribute high frequency clock signal with high reliability.

出版日期: 2017-01-01
CLC:  TN 402  
基金资助:

上海科委资助项目(14510711500,15511108100).

通讯作者: 郑立荣,男,教授,博导. ORCID: 0000-0001-9588-0239.   
作者简介: 张伟(1977—),男,博士生,从事集成电路设计的研究. ORCID: 0000-0001-9588-0239. E-mail: wei_zhang@fudan.edu.cn
服务  
把本文推荐给朋友
加入引用管理器
E-mail Alert
作者相关文章  

引用本文:

张伟, 胡友德, 郑立荣. 基于频率可调驻波振荡器的芯片时钟系统设计[J]. 浙江大学学报(工学版), 10.3785/j.issn.1008-973X.2017.01.021.

ZHANG Wei, HU You de, ZHENG Li rong. Design of chip-level clock system using frequency tunable standing-wave oscillators. JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), 10.3785/j.issn.1008-973X.2017.01.021.

[1] CHAN S C, RESTLE P J, SHEPARD K L, et al. A4.6 ghz resonant global clock distribution network [C] ∥Proceedings of IEEE International SolidState Circuits Conference (ISSCC). San Fransisco: IEEE. 2004:341-343.
[2] CHAN S C, SHEPARD K L, RESTLE P J. Design of resonant global clock distributions [C]∥ Proceedings of IEEE International Conference on Computer Design (ICCD). San Jose: IEEE, 2003: 238-243.
[3] DRAKE A, NOWKA K J, NGUYEN T Y, et al. Resonant clocking using distributed parasitic capacitance [J]. IEEE Journal of Solid-State Circuits, 2004,39(9): 1520-1528.
[4] WOOD J, EDWARDS T C, LIPA S. Rotary travelingwave oscillator arrays: a new clock technology [J]. IEEE Journal of SolidState Circuits, 2001, 36(11): 1654-1665.
[5] ANDRESS W, HAM D. Recent developments in standingwave oscillator design: review [C]∥ Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers. Forth Worth: IEEE, 2004: 119-122.
[6] MAHONY F O. 10 ghz global clock distribution using coupled standingwave oscillators [D]. Palo Alto: Stanford University, 2003.
[7] MAHONY F O, YUE C P, HOROWITZ M A, et al. A 10 ghz global clock distribution using coupled standing wave oscillators [J]. IEEE Journal of SolidState Circuits, 2003, 38(11): 1813-1820.
[8] ANDRESS W, HAM D. Standing wave oscillators utilizing waveadaptive tapered transmission lines [J]. IEEE Journal of SolidState Circuits, 2005, 40(3): 638-651.
[9] CODERO V H, KHATRI S P. Clock distribution scheme using coplanar transmission lines [C]∥ DATE’08. Munich: IEEE, 2008: 985-990.
[10] MANDAL A, KARKALA V, KHATRI S, et al.Interconnected tile standing wave resonant oscillator based clock distribution circuits [C]∥ 24th Annual Conference on VLSI Design. Chennai: IEEE, 2011: 82-87.
[11] GAUTHAUS M R, TASKIN B. Highperformance, lowpower resonant clocking: embedded tutorial[C]∥ IEEE/ACM International Conference on ComputerAided Design. San Jose: IEEE, 2012: 742-745.
[12] HONKOTE V, TASKIN B. Skew analysis and design methodologies for improved performance of resonant clocking [C]∥ 2009 International SoC. Busan: IEEE, 2009: 165-168.
[13] HONKOTE V, NAGARAJAN R D. Process variation sensitivities of rotary traveling wave and mobius standing wave oscillators [C]∥  International Symposium onElectronic System Design. Singapore: IEEE, 2013: 610.
[14] KARKALA V, BOLLAPALLI K C,GARG R, et al. A PLL design based on a standing wave resonant oscillator [C]∥ IEEE International Conference onComputer Design (ICCD). Lake Tahoe: IEEE, 2009: 511-516.
[15] MANDAL A,BOLLAPALLI K C,JAYAKUMAR N,et al. A lowjitter phaselocked resonant clock generation and distribution scheme [C]∥ IEEE 31st International Conference on Computer Design (ICCD). Asheville: IEEE, 2013: 487-490.
[16] BUNCH R L, RAMAN S. Largesignal analysis of MOS varactors in CMOSGm LC VCOs [J]. IEEE Journal of SolidState Circuits, 2003, 38(8): 1325-1332.
[17] SHEN Meigen, ZHENG LiRong, TJUKANOFF E, et al. Concurrent chip package design for global clock distribution network using standing wave approach[C]∥ 6th International Symposium on Quality of Electronic Design. San Jose: IEEE, 2005: 573-578

[1] 苏梦瑶, 陈旭斌, 邱仅朋, 王志宇, 刘家瑞, 陈华, 尚永衡,刘东栋, 郁发新. 抗单粒子翻转的高可靠移位寄存器设计[J]. 浙江大学学报(工学版), 2016, 50(4): 792-798.
[2] 井凯,庄奕琪,李振荣,吕育泽. 适用于802.11a的低噪声放大器设计[J]. 浙江大学学报(工学版), 2015, 49(3): 476-481.
[3] 孟昕,沈海斌,严晓浪. 基于XML Schema的细粒度SoC设计复用方法[J]. J4, 2011, 45(3): 486-494.
[4] 孟昕, 沈海斌, 严晓浪. 基于数据流的SoC性能建模方法及实现[J]. J4, 2011, 45(2): 314-322.
[5] 孟昕, 沈海斌, 严晓浪. MetaHDL: 面向自动推断和参数追踪硬件描述域特定语言[J]. J4, 2010, 44(6): 1079-1085.