Please wait a minute...
浙江大学学报(工学版)
J4  2013, Vol. 47 Issue (9): 1559-1565    DOI: 10.3785/j.issn.1008-973X.2013.09.007
计算机技术，无线电电子学     
音频Delta-Sigma数模转换器中
高性能数字前端模块设计
赵津晨,吴晓波,赵梦恋
浙江大学 超大规模集成电路设计研究所, 浙江 杭州 310027
Design of an efficient digital front-end for audio delta-sigma digital-to-analog converter
ZHAO Jin-chen, WU Xiao-bo, ZHAO Meng-lian
Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China
 全文: PDF  HTML
摘要：

为适应现代便携式音频设备高音质、微型化与低功耗的要求,提出一种面积优化的高精度delta-sigma数模转换器数字前端模块设计.采用改进型公共子式消除（CSE）算法构建有限冲击响应（FIR）内插滤波器,增加公共子式的利用率,以降低系统硬件开销与芯片面积；并采用一种新型双向循环移位数据加权平均（DCS-DWA）技术,可在不引入寄生音调的前提下抑制三阶四比特量化Delta-Sigma调制器的匹配误差,提高了系统的信噪失真比（SNDR）.该模块在中芯国际0.18 μm 1P6M标准CMOS工艺下流片,核心芯片面积为0.42 mm2,峰值SNDR与动态范围（DR）分别达到103.2 dB和104.4 dB.在1.5 V电源电压下,系统功耗为0.12 mW.以上结果表明主要的设计目标均已实现．
Abstract:

An area-efficient and high precision digital front-end of audio delta-sigma digital-to-analog converters (DAC) was presented to meet the increasing demands of modern audio equipments on high-fidelity, portability and low power consumption. An improved common subexpression elimination (CSE) method, which increased the utilization rate of common subexpressions and decreased the hardware overhead and die area, was proposed to implement the finite impulse response (FIR) interpolator. Besides, a novel data weighted averaging (DWA) technique named as dual cycle shift DWA (DCS-DWA) was applied to a feedforward 3rd-order delta-sigma modulator with a 4-bit quantizer to eliminate the mismatch errors while no signal-dependent tones were introduced into the modulation loop, and as a result the signal-to-noise distortion ratio (SNDR) of the system was improved. The prototype of the digital front-end was implemented in a standard SMIC CMOS 0.18 μm 1P6M process, and the core area was 0.42 mm2. The measurement results showed that the peak SNDR of the digital front-end was 103.2 dB, and the dynamic range (DR) was 104.4 dB for the audio signal bandwidth of 20 kHz. In addition, the system power consumption was reduced to 0.12 mW in a supply voltage of 1.5 V. It has been proven that the main experimental results are consistent with the expectations well．
出版日期: 2013-09-01
基金资助:

国家自然科学基金资助项目(60906012).
通讯作者: 赵梦恋，女，副教授．     E-mail: zhaoml@vlsi.zju.edu.cn
作者简介: 赵津晨(1985-)，男，博士生，从事低功耗混合信号芯片设计研究．E-mail: zhaojc@vlsi.zju.edu.cn
服务　　
把本文推荐给朋友
加入引用管理器
E-mail Alert
RSS
作者相关文章　　

引用本文:

赵津晨,吴晓波,赵梦恋. 音频Delta-Sigma数模转换器中
高性能数字前端模块设计[J]. J4, 2013, 47(9): 1559-1565.

ZHAO Jin-chen, WU Xiao-bo, ZHAO Meng-lian. Design of an efficient digital front-end for audio delta-sigma digital-to-analog converter. J4, 2013, 47(9): 1559-1565.

链接本文:

http://www.zjujournals.com/eng/CN/ 10.3785/j.issn.1008-973X.2013.09.007    或    http://www.zjujournals.com/eng/CN/Y2013/V47/I9/1559

［1］ NORSWORTHY S R, SCHREIER R, TEMES G C. Delta-sigma data converters—theory, design, and simulation ［M］. New York: IEEE Press, 1997．
［2］ MARTINEZ-PEIRO M, BOEMO E I, WANHAMMAR L. Design of high-speed multiplierless filters using a nonrecursive signed common subexpression algorithm ［J］. IEEE Transactions on Circuits and Systems II, 2002, 49(3): 196-203．
［3］ BAIRD R T, FIEZ T S. Improved ΔΣ DAC linearity using data weighted averaging ［C］∥ Proceedings of the 1995 IEEE International Symposium on Circuits and Systems. Seattle, USA: IEEE, 1995: 13-16．
［4］ AVIZIENIS A. Signed digit number representation for fast parallel arithmetic ［J］. IRE Transactions on Electronic Computers, 1961, EC-10(3): 389-400．
［5］ JANG Y, YANG L. Low-power CSD linear phase FIR filter structure using vertical common subexpression ［J］. Electronics Letters, 2002, 38(15): 777-779．
［6］ HAMOUI A A, MARTIN K. Linearity enhancement of multibit Δ-Σ modulators using pseudo data-weighted averaging ［C］∥ IEEE International Symposium on Circuits and Systems. Scottsdale, USA: IEEE, 2002: III-285–III-288．
［7］ VLEUGELS K, RABII S, WOOLEY B A. A 25 V sigma-delta modulator for broadband communications applications ［J］. IEEE Journal of Solid-State Circuits, 2001, 36(12): 1887-1899．
［8］ WANG R. A multi-bit delta sigma audio digital-to-analog converter ［D］. Corvallis: Oregon State University, 2006．
［9］ LEE K, MENG Q, SUGIMOTO T, et al. A 08 V, 26 mW, 88 dB Dual-channel audio delta-sigma D/A converter with headphone driver ［J］. IEEE Journal of Solid-State Circuits, 2009, 44(3): 916-927．
［10］ ANNOVAZZI M, COLONNA G, GANDOLFI G, et al. A low-power 98 dB multibit audio DAC in a standard 33 V 035 μm CMOS technology ［J］. IEEE Journal of Solid-State Circuits, 2002, 37(7): 825-834．
［11］ COLONNA G, ANNOVAZZI M, BOARIN G, et al. A 022 mm2 725 mW per-channel audio stereo-DAC with 97 dB DR and 39 dB SNRout ［J］. IEEE Journal of Solid-State Circuits, 2005, 40(7): 1491-1498．
［12］ BASCHIROTTO A, BOLLATI G, COLONNA G, et al. A 94dB-SNR -76dB-THD high-efficiency hybrid audio power-DAC for loudspeaker (4Ω/8Ω) and earphone (16Ω/32Ω) ［C］∥ Proceedings of the ESSCIRC, 2010. Seville, Spain: IEEE, 2010: 226-229．
［13］ LEE H, SEOK C, KIM B, et al. A self-calibration 103 dB SNR stereo audio DAC with true-GND class-D headphone drivers in 45nm CMOS ［C］∥ 2010 International SoC Design Conference (ISOCC). Seoul, Korea: IEEE, 2010: 336-337．
No related articles found!