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固定极性Reed-Muller电路最佳延时极性搜索 |
汪鹏君1, 王振海1, 陈耀武2, 李辉1 |
1. 宁波大学 电路与系统研究所,浙江 宁波 315211;
2. 浙江大学 数字技术及仪器研究所,浙江 杭州 310027 |
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Searching the best polarity for fixed polarity Reed-Muller
circuits based on delay model |
WANG Peng-jun1, WANG Zhen-hai1, CHEN Yao-wu2, LI Hui1 |
1. Institute of Circuits and Systems, Ningbo University, Ningbo 315211, China;
2. Institute of Advanced Digital Technologies and Instrumentation, Zhejiang University, Hangzhou 310027, China |
引用本文:
汪鹏君, 王振海, 陈耀武, 李辉. 固定极性Reed-Muller电路最佳延时极性搜索[J]. J4, 2013, 47(2): 361-366.
WANG Peng-jun, WANG Zhen-hai, CHEN Yao-wu, LI Hui. Searching the best polarity for fixed polarity Reed-Muller
circuits based on delay model. J4, 2013, 47(2): 361-366.
链接本文:
http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2013.02.026
或
http://www.zjujournals.com/eng/CN/Y2013/V47/I2/361
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WANG Peng-jun, LI Hui, WU Wen-jin, et al. Application of quantum genetic algorithm in searching for best polarity of multi output Reed-Muller logic circuits [J]. Acta Electronica Sinica, 2010, 38(5): 1058-1063.
[8] DAI Jing, ZHANG Hui-hong. A novel quantum genetic algorithm for area optimization of FPRM circuits [C]∥ Proceedings of International Symposium on Intelligent Information Technology Application. NanChang: IEEE, 2009: 408-411.
[9] WANG Peng-jun, LU Jin-gang, CHEN Ken, et al. Low power polarity conversion based on the whole annealing genetic algorithm [J]. Journal of Semiconductors, 2008, 29(2): 298-303.
[10] FUJITA M, MURGAI R. Delay estimation and optimization of logic circuits: a survey [C]∥ Proceedings of the Asia and South Pacific Design Automation Conference. Chiba: IEEE, 1997: 25-30.
[11] YANG Meng, WANG Ling-li, TONG Jia-rong, et al. Techniques for dual forms of Reed-Muller expansion conversion [J]. Integration, the VLSI Journal, 2008, 41(1): 113-122.
[12] YANG H, TAN E C. Optimization of multi-output fixed-polarity Reed-Muller circuits using the genetic algorithm [J]. International Journal of Electronics, 1999, 86(6): 663-670. |
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