Please wait a minute...
浙江大学学报(工学版)
J4  2011, Vol. 45 Issue (5): 835-839    DOI: 10.3785/j.issn.1008-973X.2011.05.010
电气工程     
考虑非均匀温度分布的RLC互连延时
王增,杨银堂,董刚,李建伟
西安电子科技大学 微电子所， 宽禁带半导体材料与器件教育部重点实验室,陕西 西安 710071
RLC interconnect delay with nonuniform temperature distribution
WANG Zeng, YANG Yin-tang, DONG Gang, LI Jian-wei
Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and
Devices, Microelectronics Institute, Xidian University, Xi'an 710071, China
 全文: PDF  HTML
摘要：

为解决高性能集成电路设计中互连延时估算精确较低的问题,在分析互连温度分布的基础上,提出一种考虑非均匀温度分布效应的互连延时模型,该模型基于电感转化为等效电阻的思想,将互连电感效应整合到所提模型中.针对65 nm工艺,讨论3种典型的非均匀温度分布以及电感效应对互连延时的具体影响,以电路模拟程序Hspice为参照,将所提模型与同类模型进行比较,仿真结果显示本文模型更为精确,最大误差不超过3.3%.同时本文模型具有闭合的解析形式,公式简洁,可有效地提高计算效率.
Abstract:

In order to improve the bad accuracy of interconnect delay estimation, a new interconnect delay model considering the nonuniform temperature distribution was presented on the basis of the analysis of temperature distribution along interconnect in this paper. The proposed model incorporated interconnect inductance effect based on the thought of considering inductance as equivalent resistance. For 65 nm process technology, the paper discussed the impacts of three kind of nonunifor temperature distribution and inductance effect on interconnect delay. Results show that our proposed model with less than 3.3% error is more accurate than the other available similar models by comparing the results of Hspice. At the same time, the proposed analytical model with simple expression has closedform expression and improves the calculation efficiency．
出版日期: 2011-11-24
:  TN 405.97  
基金资助:

国家自然科学基金项目(60606006)；国家杰出青年基金项目(60725415).
通讯作者: 杨银堂，男，教授，博导.     E-mail: yangyt@xidian.edu.cn
作者简介: 王增(1977-)，男，山东青岛人，博士生，从事与温度相关的互连建模与仿真研究.E-mail: fire5water1@hotmail.com
服务　　
把本文推荐给朋友
加入引用管理器
E-mail Alert
作者相关文章　　

引用本文:

王增,杨银堂,董刚,李建伟. 考虑非均匀温度分布的RLC互连延时[J]. J4, 2011, 45(5): 835-839.

WANG Zeng, YANG Yin-tang, DONG Gang, LI Jian-wei. RLC interconnect delay with nonuniform temperature distribution. J4, 2011, 45(5): 835-839.

链接本文:

https://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2011.05.010    或    https://www.zjujournals.com/eng/CN/Y2011/V45/I5/835

［1］ KUMAR R, KURSUN V. Reversed Temperature dependent propagation delay characteristics in nanometer CMOS circuits ［J］. IEEE transactions on Circuits and systems II, 2006, 53(10): 1078-1082.
［2］ NI Min., MEMIK S O. Self heatingaware optimal wire sizing under Elmore delay model ［C］∥ Europe Conference & Exhibition on Design, Automation & Test, Nice, France: SpringVerlag, 2007, 1-6.
［3］ 王增,董刚,杨银堂,等. 考虑温度分布效应的非对称RLC树时钟偏差研究［J］. 物理学报, 2010, 59(8)：5646-5651.
WANG.Zeng,DONG Gang, YANG Yintang, et al.Study on clock skew of unsymmetrical RLC interconnect tree with temperature distribution \
[J\].Acta Physica Sinica,2010,59(8):5646-5651.
［4］ AJAMI A H, BANERJEE K, PEDRAM M. Modeling and analysis of nonuniform substrate temperature effects on global ULSI Interconnects ［J］. IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, 2005, 24(6): 849-861.
［5］ CHEN Guoqing, FRIEDMAN E G. An RLC interconnect model based on fourier analysis ［J］. IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, 2005, 24(2): 170-183.
［6］ HOSEINI F A, MSOUMI N. Fast estimation of interconnects delay in RLC trees using neural network ［C］∥ MWSCAS 2007 50th Midwest Symposium on Circuits and Systems. Montreal, Canada: SpringerVerlag, 2007, 1309-1312.
［7］ JIANG Zhanyuan, HU Shiyan, HU Jiang, et al. A new RLC buffer insertion algorithm ［C］∥ Proc. of IEEE/ACM International Conference on ComputerAided Design, New York: Institute of Electrical and Electronics Engineers Press, 2006, 553-557.
［8］ KIM S Y, WONG S S. Closedform RC and RLC delay models considering input rise time ［J］. IEEE Transactions on Circuits and Systems I: Regular Papers, 2007, 54(9):2001-2010.
［9］ ANTONINI G, FERRI G. Laddernetworkbased model for delay determination in coupled interconnects ［J］. IEE ProceedingsScience on Measurement and Technology, 2006, 153(2): 64-72.
［10］ RAVINDRA J V R, SRINIVAS M B. Delay and slew analysis of VLSI interconnects using difference model approach ［C］∥ MWSCAS 2007 50th Midwest Symposium on Circuits and Systems, Montreal, Canada: SpringerVerlag, 2007, 1313-1315.
［11］ CHAPMAN A J. Fundamental of heat transfer ［M］. 4th ed. New York: Mcmillan, 1984: 147．
［12］ IM S, BANERJEE K. Full chip thermal analysis of planar (2D) and vertically integrated (3D) highperformance Ics ［C］∥ Proc. of International Electron Device Meeting. San Francisco, California, USA: the University of Hong Kong Press, 2000, 727-730.
［13］ LIN Shengchih, CHRYSLER G, MAHAJAN R, et al. A selfconsistent substrate thermal profile estimation technique for nanoscale ICs—part II: implementation and implications for power estimation and thermal management ［J］. IEEE Transaction on Electron devices, 2007,54(12): 3351-3360.
［14］ TSAI Chinghan, KANG Sungmo. CellLevel placement for improving substrate thermal distribution ［J］. IEEE transactions on computeraided design of integrated circuits and systems, 2000, 19(2): 253-266.
［15］ VENKATESAN R, DAVIS J A, MEINDL J D. Compact distributed RLC interconnect models part III: transients in single and coupled lines with capacitive load termination ［J］. IEEE transactions on Electron Devices, 2003, 50(4): 1081-1093.
［16］ ZHOU Mingcui, LIU Wentai, Sivaprakasam M. A closedform delay formula for onchip RLC interconnects in currentmode signaling ［C］∥ IEEE International Symposium on Circuits and Systems. Kobe Japan: CRC, 2005, 2, 1082-1085.
［17］ ESIA, JEITA, KSIA, et al. International Technology Roadmap for Semiconductors ［EB/OL］. ［2007］. http:∥www.itrs.net/Links/2007ITRS/Home2007.htm
No related articles found!