Please wait a minute...
浙江大学学报(工学版)
J4  2009, Vol. 43 Issue (11): 1970-1974    DOI: 10.3785/j.issn.1008-973X.2009.11.005
自动化技术、计算机技术     
新型电流型CMOS四值边沿触发器设计
杭国强1,应时彦2
（1.浙江大学 信息与通信工程研究所,浙江省综合信息网技术重点实验室,浙江 杭州 310027；
2.浙江工业大学 信息工程学院,浙江 杭州 310014）
Novel current-mode CMOS quaternary edge-triggered flip-flops
HANG Guo-qiang1, YING Shi-yan2
(1. Institute of Information and Communication Engineering, Zhejiang Provincial Key Laboratory of Information Network Technology, Zhejiang University, Hangzhou 310027, China;
2. College of Information Engineering, Zhejiang University of Technology, Hangzhou 310014, China)
 全文: PDF(585 KB)   HTML
摘要：

提出3种应用于多值逻辑系统的电流型触发器设计,包括四值主从结构触发器、单闩锁单边沿触发器和单闩锁双边沿触发器.采用电流阈值控制技术简化这些电路的结构.单个锁存器的四值单边沿和双边沿触发器分别利用时钟信号的1个边沿和2个边沿后产生的窄脉冲使锁存器瞬时导通,实现取样求值.单闩锁结构的触发器不仅可以简化电路结构,更重要的是大大降低了电流型触发器的直流功耗.在保持相同数据吞吐量的条件下,应用双边沿触发器可以使时钟信号的频率减半,从而降低时钟网络的动态功耗.采用TSMC 0.25 μm CMOS工艺参数的HSPICE模拟结果验证了所提出设计方案的有效性.
Abstract:

Three new current-mode CMOS flip-flops applied to multiple-valued logic (MVL) systems were presented, including quaternary master-slave flip-flop, one-latch quaternary single edge-triggered (1L-QSET) flip-flop and one-latch quaternary double edge-triggered flip-flop (1L-QDET). The constructions of the circuits were simplified by employing the current threshold-controlling technique. In the 1L-QSET and 1L-QDET configurations, data are sampled into the latch during a transparency period for one edge or each edge of the clock signal, respectively. In comparison with the current-mode quaternary master-slave flip-flop, the one-latch configurations reduce the transistor count and lower the static power consumption. For a given throughput, the clock frequency can be halved using the double edged-triggered flip-flops, therefore the dynamic power dissipation of the clock network can be reduced. The HSPICE simulation using TSMC 0.25 μm CMOS technology validated the effectiveness of the proposed approach. Finally, the simulated results of the propagation delay and the power dissipation were compared among the proposed quaternary flip-flops．
出版日期: 2009-11-01
:  TN 432  
基金资助:

国家自然科学基金资助项目（60971061);浙江省自然科学基金资助项目（Y105124，Y106375）.
作者简介: 杭国强（1968-），男，浙江桐乡人，副教授，博士，从事低功耗集成电路设计及多值逻辑电路研究.
服务　　
把本文推荐给朋友
加入引用管理器
E-mail Alert
RSS
作者相关文章　　

引用本文:

杭国强, 应时彦. 新型电流型CMOS四值边沿触发器设计[J]. J4, 2009, 43(11): 1970-1974.

HANG Guo-Jiang, YING Shi-Pan. Novel current-mode CMOS quaternary edge-triggered flip-flops. J4, 2009, 43(11): 1970-1974.

链接本文:

http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2009.11.005    或    http://www.zjujournals.com/eng/CN/Y2009/V43/I11/1970

[1] TANNO K, ISHIZUKA O. Survey of multiple-valued circuit technologies [C]∥ International Workshop on Post-Binary ULSI Systems. Boston: IEEE, 2002．
[2] CURRENT K W. Current-mode CMOS multiple-valued logic circuits [J]. IEEE Journal of Solid State Circuits, 1994, 29(2): 95-107．
[3] ISHIZUKA O, OHTA A, TANNNO K, et al. VLSI design of a quaternary multiplier with direct generation of partial products [C]∥ Proceedings of the International Symposium on Multiple-Valued Logic. Antigonish: IEEE, 1997: 169-174．
[4] IKE T, HANYU T, KAMEYAMA M. Fully source-coupled logic based multiple-valued VLSI [C]∥ Proceedings of the International Symposium on Multiple- Valued Logic. Los Alamitos: IEEE, 2002: 270-275．
[5] 杭国强,任洪波,吴训威. 基于控阈技术的四值电流型CMOS电路设计[J]. 半导体学报, 2002, 23(5): 523-528.
HANG Guo-qiang, REN Hong-bo, WU Xun-wei. Design of current-mode CMOS quaternary circuits based on threshold-controllable technique [J]. Chinese Journal of Semiconductors, 2002, 23(5): 523-528．
[6] 杭国强. 基于控阈技术的电流型CMOS全加器的通用设计方法[J]. 电子学报, 2004, 32(8): 1367-1369．
HANG Guo-qiang. Universal design method for current-mode CMOS adders based on threshold-controllable technique [J]. Acta Electronica Sinica, 2004, 32(8): 1367-1369．
[7] ABD-EL-BARR M, AL-MUTAWA A. A new improved cost-table-based technique for synthesis of 4-valued unary functions implemented using current-mode CMOS circuits [C]∥ Proceedings of the International Symposium on Multiple-Valued Logic. Warsaw: IEEE, 2001: 15-20．
[8] MOCHIZUKI A, HANYU T. Low-power multiple- valued current-mode logic using substrate bias control [J]. IEICE Transactions on Electronics, 2004, E87-C(4): 582-588．
[9] 杭国强,吴训威. 一种单锁存器CMOS 三值D型边沿触发器设计[J]. 电子学报,2002, 30(5): 760-762.
HANG Guo-qiang, WU Xun-wei. CMOS ternary D-type edge-triggered flip-flop using one latch [J]. Acta Electronica Sinica, 2002, 30(5): 760-762．
[10] KIM C, KANG S M. A low-swing clock double-edge triggered flip-flop [J]. IEEE Journal of Solid-State Circuits, 2002, 37(5): 648-652．
[1] 雷鑑铭, 胡北稳, 桂涵姝, 张乐. 采用新型低成本共模反馈电路的全差分运放设计[J]. J4, 2013, 47(10): 1777-1783.
[2] 杭国强, 李锦煊, 王国飞. 新型钟控神经元MOS采样/保持电路[J]. J4, 2012, 46(2): 333-337.
[3] 韩雁 , 廖璐 , 黄小伟 , 张昊 , 王昊. 多比特量化的音频DAC中模拟电路的设计[J]. J4, 2011, 45(9): 1571-1575.
[4] 肖林荣, 陈偕雄, 应时彦. 基于模块化技术的最佳ULG.2的QCA电路设计[J]. J4, 2011, 45(6): 1032-1037.
[5] 徐扬, 沈继忠. 基于门控时钟的低功耗时序电路设计新方法[J]. J4, 2010, 44(9): 1724-1729.
[6] 徐科君, 许文曜, 沈继忠, 等. 双电压动态可重构FPGA任务模型及调度算法[J]. J4, 2010, 44(2): 300-304.
[7] 章丹艳, 吴晓波, 赵梦恋, 等. 光伏电池最大功率点跟踪芯片的设计[J]. J4, 2009, 43(11): 2000-2005.