We propose an accurate model to describe the I-V characteristics of a sub-90-nm metal–oxide–semiconductor field-effect transistor (MOSFET) in the linear and saturation regions for fast analytical calculation of the current. The model is based on the BSIM3v3 model. Instead of using constant threshold voltage and early voltage, as is assumed in the BSIM3v3 model, we define these voltages as functions of the gate-source voltage. The accuracy of the model is verified by comparison with HSPICE for the 90-, 65-, 45-, and 32-nm CMOS technologies. The model shows better accuracy than the nth-power and BSIM3v3 models. Then, we use the proposed I-V model to calculate the read static noise margin (SNM) of nano-scale conventional 6T static random-access memory (SRAM) cells with high accuracy. We calculate the read SNM by approximating the inverter transfer voltage characteristic of the cell in the regions where vertices of the maximum square of the butterfly curves are placed. The results for the SNM are also in excellent agreement with those of the HSPICE simulation for 90-, 65-, 45-, and 32-nm technologies. Verification in the presence of process variations and negative bias temperature instability (NBTI) shows that the model can accurately predict the minimum supply voltage required for a target yield.

关键词： Modeling,  Nano-scale,  Process variation,  Read static noise margin (SNM),  SRAM