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浙江大学学报(工学版)
Journal of ZheJiang University (Engineering Science)  2021, Vol. 55 Issue (3): 571-577    DOI: 10.3785/j.issn.1008-973X.2021.03.018
    
Design of low power differential multiplexing beamformer
Lin-nan LI(),Wei ZHANG*(),Yan-jie DANG,Tai-an LI
College of Microelectronic, Tianjin University, Tianjin 300072, China
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Abstract  

A new differential beamformer architecture was proposed to solve the problems of high power consumption and large scale of the traditional multiplexing network architecture, in order to make direct connection between beamformer and differential feed antennas, suppress noise and interference. The differential active delay units were used to replace the passive delay units and buffers on one-way path in the traditional architecture, and combined with the differential passive delay units on two-way path to form the fixed delay time differences among different paths. Based on HHNEC 0.18 μm CMOS technology, a four-input-four-output beamformer was designed to verify the proposed architecture. Simulation showed that in the 0.5—1.5 GHz bandwidth, the resolution of the delay network was 80 ps, the maximum delay value was 720 ps, the delay variation root mean square value was 29.7 ps, the output reflection coefficient of the circuit was lower than –23 dB, the input reflection coefficient was lower than ?10 dB, the in-band synthesis gain was 18—21 dB, the layout area was 2.96 mm × 3.22 mm, and the total power consumption at 1.8 V supply voltage was 303 mW. Experimental results show that the proposed structure has the advantages of high accuracy, moderate scale, low power consumption and low complexity.

Key words： analog beamforming      true time delay      low power consumption      differential multiplexing      group delay     
Received: 19 February 2020      Published: 25 April 2021
CLC:  TN 432  
Fund:  国家重点研发计划资助项目（2016YFE0100400）
Corresponding Authors: Wei ZHANG     E-mail: lilinnan@tju.edu.cn;tjuzhangwei@tju.edu.cn
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Lin-nan LI
Wei ZHANG
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Tai-an LI
Cite this article:

Lin-nan LI,Wei ZHANG,Yan-jie DANG,Tai-an LI. Design of low power differential multiplexing beamformer. Journal of ZheJiang University (Engineering Science), 2021, 55(3): 571-577.

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http://www.zjujournals.com/eng/10.3785/j.issn.1008-973X.2021.03.018     OR     http://www.zjujournals.com/eng/Y2021/V55/I3/571


低功耗差分复用波束合成器的设计

为了实现波束合成器与差分馈电天线的直接连接，抑制噪声与干扰，针对传统复用网络架构的高功耗、大面积问题，提出新型差分波束合成架构. 采用差分有源延时单元代替传统架构单向通路上的无源延时单元和缓冲器，与双向通路上的差分无源延时单元结合，形成不同通路之间的固定延时差. 基于 HHNEC 0.18 μm CMOS 工艺，设计四输入四输出的波束合成器对所提架构进行验证. 仿真结果表明，在0.5~1.5 GHz带宽内，延时网络的分辨率为80 ps，最大延时值为720 ps，延时浮动均方根值为29.7 ps，电路的输出反射系数低于?23 dB，输入反射系数低于?10 dB，带内增益为18~21 dB，版图面积为2.96 mm×3.22 mm，在1.8 V电源电压下，总功耗为303 mW. 实验结果证明所提结构具有高精度、面积适中、低功耗和低复杂度的优点.


关键词： 模拟波束合成,  真延时,  低功耗,  差分复用,  群延时 
Fig.1 Beamforming schematic diagram
Fig.2 Common beamforming architectures
Fig.3 New differential multiplexing network architecture
输入端口 输出端口
P1 P2 P3 P4
A1 2 $ \tau $ $ 0 $ $ 5\tau $ $ 9\tau $
A2 $ 3\tau $ $ 3\tau $ $ 4\tau $ $ 6\tau $
A3 $ 4\tau $ $ 6\tau $ $ 3\tau $ $ 3\tau $
A4 $ 5\tau $ $ 9\tau $ $ 2\tau $ $ 0 $
Tab.1 Delay difference from four input ports to four output ports
Fig.4 Comparison of LC passive delay structures
参数 数值 单位 参数 数值 单位
$ {L}_{\mathrm{D}\mathrm{F}1} $ 1.96 nH $ {C}_{1} $ 404.88 fF
$ {L}_{\mathrm{D}\mathrm{F}2} $ 2.15 nH $ {C}_{2} $ 65.56 fF
$ {L}_{3} $ 339.41 pH $ {C}_{3} $ 562.72 fF
$ {L}_{4} $ 2.75 nH $ {C}_{4} $ 400.00 fF
$ {C}_{5} $ 400.00 fF
Tab.2 Capacitance and inductance required by three structures
Fig.5 Differential passive delay circuit and its equivalent circuit
Fig.6 Comparison of transmission function between ideal delay and first-order all pass filter
Fig.7 Circuit diagram of differential active delay
Fig.8 Half circuit diagram of differential LNA
Fig.9 Half circuit diagram of buffer
Fig.10 Layout of proposed beamformer
Fig.11 Post simulation results of beamformer’s parameters
Fig.12 Simulation results of beamformer directional diagram
类别 工艺 带宽/GHz 真延时技术 电路结构 cd Pout rd /ps Rd /ps rdf /% Gb /dB P /mW S /mm2
注：*根据仿真曲线预估得到，**根据延时RMS值计算得到
文献[12] 0.18 μm CMOS 0.50~1.50 LC 单端复用网络 4 4 0~720 80 ? 26 544 13.40
文献[18] 0.18 μm CMOS 0.30~1.00 gm-C 差分链路结构 4 4 0~1 030 103 2.4 25 396 3.80
文献[20] 65.00 nm CMOS 24.25~26.65 gm-C 单端链路结构 1 1 0~13 1 5.8 ? 8 ?
文献[21] 0.18 μm CMOS 0.50~3.00 LC与gm-C 单端链路结构 1 1 0~92 4* 2.4 ?6~?4 25 0.63
本文 0.18 μm CMOS 0.50~1.50 LC与gm-C 差分复用网络 4 4 0~720 80 4.1** 18~21 303 9.60
Tab.3 Main performance comparison of beamformers
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