Implementation of direct digital frequency synthesizer based on three-step rotation coordinate rotation digital computer algorithm

doi:10.3785/j.issn.1008-973X.2019.10.021

Journal of ZheJiang University (Engineering Science)

2019, Vol. 53

Issue (10): 2034-2040 DOI: 10.3785/j.issn.1008-973X.2019.10.021

Communication technology

Implementation of direct digital frequency synthesizer based on three-step rotation coordinate rotation digital computer algorithm

Ya-yun ZHANG(

),Jia-rui LIU*(

),Zhi-yu WANG,Jiong-jiong MO,Fa-xin YU

College of Aeronautics and Astronautics, Zhejiang University, Hangzhou 310027, China

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Abstract

A high precision and low output delay coordinate rotation digital computer (CORDIC) algorithm based on three-step rotation mechanism was proposed. The operation of the residual rotation angle was avoided by binary to bipolar recoding of the input angle, the number of iterations was compressed by three-step rotation mechanism, and the number of iterations and output delay were reduced by combining with merging iteration technique. The three-step rotation CORDIC algorithm and pipeline iterative algorithm were implemented by taking 16-bit output bit-width as an example. The simulation results show that the three-step rotation CORDIC algorithm improves the output accuracy, reduces the input-output delay by 75%, and reduces the hardware overhead by 29.2% compared with the pipeline iterative algorithm. The direct digital frequency synthesizer (DDFS) with a phase accumulator of 24 bits bit-width was implemented based on the three-step rotation CORDIC algorithm, and the multi-input adder was optimized with the addition tree structure in order to improve the circuit frequency. The simulation results showed that the maximum amplitude error of the algorithm was 8.24 × 10^?6, and the output delay was 38.5 ns.

Key words： coordinate rotation digital computer (CORDIC) binary to bipolar recoding three-step rotation merging iteration adder tree field programmable gate array

Received: 22 August 2018 Published: 30 September 2019

CLC:	TN 431
	TN 911

Corresponding Authors: Jia-rui LIU E-mail: yyzhangstu@zju.edu.cn;jrliu@zju.edu.cn

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	Ya-yun ZHANG
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Ya-yun ZHANG,Jia-rui LIU,Zhi-yu WANG,Jiong-jiong MO,Fa-xin YU. Implementation of direct digital frequency synthesizer based on three-step rotation coordinate rotation digital computer algorithm. Journal of ZheJiang University (Engineering Science), 2019, 53(10): 2034-2040.

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http://www.zjujournals.com/eng/10.3785/j.issn.1008-973X.2019.10.021 OR http://www.zjujournals.com/eng/Y2019/V53/I10/2034

基于三步旋转坐标旋转数字计算机算法的直接数字频率综合器实现

提出基于三步旋转机制的高精度低时延坐标旋转数字计算机 (CORDIC)算法. 该算法通过对输入角度进行二极化重编码来免除剩余旋转角度的运算，利用三步旋转机制对迭代次数进行压缩，结合合并迭代技术进一步减少迭代次数，降低输出时延. 以16位输出位宽为例，对三步旋转CORDIC算法和流水线迭代式算法进行实现，仿真结果表明：三步旋转CORDIC算法与流水线迭代式算法相比，改善了输出精度，输入到输出的时延降低了75%，硬件开销下降了29.2%. 基于三步旋转CORDIC算法，实现了相位累加器位宽为24的直接数字频率综合器 (DDFS)；使用加法树结构对多输入加法器进行优化，以提高电路工作频率. 仿真结果表明，该算法的最大幅度误差为8.24 × 10^?6，输出时延为38.5 ns.

关键词： 坐标旋转数字计算机 (CORDIC), 二极化重编码, 三步旋转, 合并迭代, 加法树, 现场可编程门阵列

Fig.1 Vector rotation diagram

Fig.2 Schematic diagram of three-step rotation structure

Fig.3 Block diagram of three-step rotation algorithm realization

Tab.1 Performance comparison of two algorithms

Fig.4 DDFS structure based on three-step rotation

Fig.5 Schematic diagram of three-stage addition tree

Fig.6 Modelsim simulation diagram

Fig.7 Sine and cosine absolute error of three-step rotation CORDIC algorithm

Fig.8 Spectrum of output signal when output frequency is 120 MHz

Tab.2 Comparison of maximum amplitude error, output delay and hardware consumption of four schemes


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