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浙江大学学报(工学版)
JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE)  2018, Vol. 52 Issue (3): 531-536    DOI: 10.3785/j.issn.1008-973X.2018.03.015
Computer and Communication Technology     
Pre-charge read scheme for phase change memory
LEI Yu, CHEN Hou-peng, WANG Qian, LI Xi, HU Jia-jun, SONG Zhi-tang
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
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Abstract  

The speed limit of the conventional read scheme of phase change memory was analyzed, based on which a pre-charge scheme was proposed aiming at speed up the read speed. As soon as the chip was switched to the reading mode, the local bit lines were charged to the pre-charge voltage. The pre-charge voltage was set at the average of local bit line voltages when reading a worst case set cell and a worst case reset cell. Designed and simulated in the SMIC 40 nm CMOS process, the read access time of 1-Mb phase change memory is 6.64 ns compared to the conventional 45.36 ns. Monte Carlo simulations show a 9.07 ns worst read access time compared to the conventional 128.1 ns. Set cell reading current is as small as 4.84 μA. Simulation results show that the proposed scheme has better process, voltage and temperature variation tolerance than the conventional scheme.

Received: 24 October 2016      Published: 11 September 2018
CLC:  TN432  
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Cite this article:

LEI Yu, CHEN Hou-peng, WANG Qian, LI Xi, HU Jia-jun, SONG Zhi-tang. Pre-charge read scheme for phase change memory. JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), 2018, 52(3): 531-536.

URL:

http://www.zjujournals.com/eng/10.3785/j.issn.1008-973X.2018.03.015     OR     http://www.zjujournals.com/eng/Y2018/V52/I3/531


相变存储器预充电读出方法

分析传统相变存储器读出方法读取速度受限的原因，提出一种预充电读出方法.该方法将本地位线充电到预充电电压后开始读取数据.预充电电压设置在第一参考电压和第二参考电压的中间值.第一参考电压为读取最高晶态电阻值的存储器件时的本地位线电压，第二参考电压为读取最低非晶态电阻值的存储器件时的本地位线电压.采用SMIC 40 nm CMOS工艺进行设计和仿真，1-Mb相变存储器的随机读取时间为6.64 ns；Monte Carlo仿真表明，最长随机读取时间为9.07 ns.传统读出方法的随机读取时间和最长随机读取时间分别为45.36 ns和128.1 ns.晶态单元读电流是4.84 μA.仿真结果表明，所提方法比传统方法能更好地抑制工艺角、电源电压和温度波动.

[1] RAO F, DING K, ZHOU Y, et al. Reducing the stochasticity of crystal nucleation to enable subnanosecond memory writing[J]. Science, 2017, eaao3212:1-10.
[2] 雷宇,陈后鹏,金荣,等. 用于相变存储器的高效开关电容电荷泵[J]. 微电子学,2015,45(3):335-339. LEI Y, CHEN H, JIN R, et al. An efficiency-enhanced SC charge pump for PCM[J]. Microelectronics, 2015,45(3):335-339.
[3] BURR G W, BRIGHTSKY M J, Sebastian A, et al. Recent progress in phase-change memory technology[J]. IEEE Journal on Emerging & Selected Topics in Circuits & Systems, 2016, 6(2):1-17.
[4] LEI Y, CHEN H, LI X, et al. An efficiency-enhanced 2X/1.5X SC charge pump with auto-adjustable output regulation for PCM[C]//International Workshop on Information Data Storage and Tenth International Symposium on Optical Storage. Changzhou:SPIE, 2016, 981807:1-7.
[5] XU Z, LIU B, CHEN Y, et al. The Improvement of Nitrogen Doped Ge2Sb2Te5 on the Phase Change Memory Resistance distributions[J]. Solid State Electronics, 2016, 116:119-123.
[6] GAO D, LIU B, Xu Z, et al. Failure analysis of nitrogen-doped Ge2Sb2Te5 phase change memory[J]. IEEE Transactions on Device and Materials Reliability, 2016, 16(1):74-79.
[7] JIN D H, KWON J W, KIM H J, et al. A 15μm-pitch, 8.7-ENOB, 13-Mcells/sec logarithmic readout circuit for multi-level cell phase change memory[J]. IEEE Journal of Solid-State Circuits, 2015, 50(10):2431-2440.
[8] YU S, CHEN P Y. Emerging memory technologies:recent trends and prospects[J]. IEEE Solid-State Circuits Magazine, 2016, 8(2):43-56.
[9] LEI Y, CHEN H, WANG Q, et al. A single-reference parasitic-matching sensing circuit for 3D cross point PCM[J]. IEEE Transactions on Circuits and Systems Ⅱ:Express Briefs, 2017, PP(99):1-5.
[10] LEE K J, CHO B H, CHO W Y, et al. A 90 nm 1.8 V 512 Mb diode-switch PRAM with 266 MB/s read throughput[J]. IEEE Journal of Solid-State Circuits, 2008, 43(1):150-162.
[11] HANZAWA S, KITAI N, OSADA K, et al. A 512kB embedded phase change memory with 416kB/s write throughput at 100μA cell write current[C]//IEEE International Solid-state Circuits Conference. San Francisco:IEEE, 2007:474-616.
[12] TSUCHIDA K, INABA T, FUJITAa K, et al. A 64Mb MRAM with clamped-reference and adequate-reference schemes[C]//IEEE International Solid-state Circuits Conference. San Francisco:IEEE, 2010:258-259.
[13] CHANG M F, WU J J, CHIEN T F, et al. 19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme[C]//IEEE International Solid-state Circuits Conference. San Francisco:IEEE, 2014:332-333.
[14] NN T, KIM J, KIM J P, et al. A double-sensing-margin offset-canceling dual-stage sensing circuit for resistive nonvolatile memory[J]. IEEE Transactions on Circuits & Systems Ⅱ Express Briefs, 2015, 62(12):1109-1113.
[15] KO J, YANG Y, KIM J, et al. Incremental bitline voltage sensing scheme with half-adaptive threshold reference scheme in MLC PRAM[J]. IEEE Transactions on Circuits & Systems I Regular Papers, 2017, 64(6):1444-1455.
[16] NA T, KIM J, SONG B, et al. An offset-tolerant dual-reference-voltage sensing scheme for deep submicrometer STT-RAM[J]. IEEE Transactions on Very Large Scale Integration Systems, 2016, 24(4):1361-1370.
[17] LEI Y, CHEN H, LI X, et al. Enhanced read performance for phase change memory using a reference column[J]. IEICE Electronics Express, 2017, 14(5):1-10.
[18] LEI Y, CHEN H, LI X, et al. Set/reset reference and parasitic matching scheme to speed up PCM read operation[J]. Electronics Letters, 2017, 53(3):144-146.
[19] FAN X, CHEN H, WANG Q, et al. Optimization of periphery circuits in a 1K-bit PCRAM chip for highly reliable write and read operations[J]. IEICE Electronics Express, 2014, 11(24):20141071-20141071.
[20] WANG Q, LI X, CHEN H, et al. Methods to speed up read operation in a 64Mbit phase change memory chip[J]. IEICE Electronics Express, 2015, 12(20):1-6.
[21] CHUNG H, JEONG B H, MIN B J, et al. A 58 nm 1.8V 1Gb PRAM with 6.4MB/s program BW[C]//IEEE International Solid-state Circuits Conference. San Francisco:IEEE, 2011:500-502.
[22] CHOI Y, SONG I, PARK M H, et al. A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth[C]//IEEE International Solid-state Circuits Conference. San Francisco:IEEE, 2012:46-48.
[23] KO J, KIM J, CHOI Y, et al. Temperature-tracking sensing scheme with adaptive precharge and noise compensation scheme in PRAM[J]. IEEE Transactions on Circuits & Systems I Regular Papers, 2015, 62(8):2091-2102.
[24] LUNG H L, MILLER C P, CHEN C J, et al. A double-data-rate-2(DDR2) interface phase-change memory with 533MB/s read -write data rate and 37.5ns access latency for memory-type storage class memory applications[C]//IEEE International Memory Workshop. Paris:IEEE, 2016:1-5.
[25] DE S G, BETTINI L, PIROLA A, et al. A 4 Mb LV MOS-selected embedded phase change memory in 90 nm standard CMOS technology[J]. IEEE Journal of Solid-State Circuits, 2011, 46(1):52-63.
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