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| ESD protection of NMOS device at different gate bias |
| ZHU Ke-han, DONG Shu-rong, HAN Yan, DU Xiao-yang |
| (Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China) |
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Abstract In salicided sub-micron CMOS technology, the electrostatic discharge (ESD) performance of NMOS device as the self-protected output buffer at uncertain gate bias was analyzed. NMOS device structures for ESD protection were designed and fabricated in a 0.35 μm CMOS process. Their ESD abilities were measured by a transmission line pulse (TLP) testing system at different gate bias. With ISE-TCAD, the electric field density distribution of the device at different gate bias was shown by transient simulation. The results show that the gate bias can degrade the second breakdown current because of more current flow at the surface ofNMOS device. When designing the snapback based gate coupled NMOS ESD protection device, the RC time constant of trigger-assisting circuit should be controlled around 50 ns.
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Published: 26 February 2010
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不同栅压下NMOS器件的静电防护性能
针对金属硅化物亚微米工艺,研究当静电自保护输出驱动中NMOS器件的栅极处于不确定电压时的静电防护能力.在0.35μm CMOS工艺下,设计不同尺寸的NMOS静电防护器件,采用传输线脉冲（TLP）测试系统测量NMOS器件在不同栅压下的电流-电压曲线.借助半导体器件仿真软件ISE-TCAD对器件进行瞬态仿真,得出在不同栅压下的电场强度分布.分析表明,栅压使得电流更趋于表面流动而降低NMOS静电防护器件的二次击穿电流.在设计回跳型栅极耦合NMOS静电防护器件时,辅助触发电路的RC时间常数应该控制在50 ns左右.
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