| Aeronautics and Astronautics Technology |
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| Design of highly reliable single event upset hardened shift register |
| SU Meng yao, CHEN Xu bin, QIU Jin peng, WANG Zhi yu, LIU Jia rui,CHEN Hua, SHANG Yong heng, LIU Dong dong, YU Fa xin |
| School of Aeronautics and Astronautics, Zhejiang University, Hangzhou 310027, China |
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Abstract A design of highly reliable shift register which can efficiently fight against the single event upset (SEU) to improve reliability and SEU tolerance of traditional shift register was presented. Bilateral resetting, bit line segregation and tri mode redundancy technologies were applied based on TSMC 0.18 μm 1.8 V 1P5M process in order to design bilateral resetting power on reset (POR) and SEU hardened dual interlocked storage cell (DICE) circuits. The SEU hardening performance of traditional shift register was completely enhanced at both aspects of schematic and layout. Transient current pulses with different linear energy transfer (LET) were injected in sensitive nodes of circuits in order to emulate the single event effects. Simulations were performed to verify the SEU tolerance of designed shift register by introducing Spectre simulator, BSIM3v3 physical model and theoretical analysis of transient circuits. The simulation results show that the proposed bilateral POR and SEU hardened DICE do not upset even when LET reaches 100 MeV·cm2/mg. Compared with traditional shift register, the presented shift register shows great improvement of SEU tolerance as well as high reliability and radiation tolerance, which can be applied for the design of CMOS chips in the field of aerospace.
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Published: 01 April 2016
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Cite this article:
SU Meng yao, CHEN Xu bin, QIU Jin peng, WANG Zhi yu, LIU Jia rui,CHEN Hua, SHANG Yong heng, LIU Dong dong, YU Fa xin. Design of highly reliable single event upset hardened shift register. JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), 2016, 50(4): 792-798.
URL:
http://www.zjujournals.com/eng/10.3785/j.issn.1008-973X.2016.04.026 OR http://www.zjujournals.com/eng/Y2016/V50/I4/792
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抗单粒子翻转的高可靠移位寄存器设计
为了提高传统移位寄存器的可靠性和耐辐射性,提出抗单粒子翻转（SEU）的高可靠移位寄存器.该设计基于TSMC 0.18 μm 1.8 V 1P5M工艺,利用双边复位、位线分离和三模冗余技术,设计双边上电复位（POR）和SEU加固双互锁存储单元（DICE）结构.从原理图和版图两个层面,对传统移位寄存器结构进行全面SEU加固.为了模拟单粒子效应,在电路敏感节点注入不同线性能量传输（LET）的瞬态电流脉冲,利用Spectre仿真器及BSIM3v3物理模型,结合瞬态电路分析理论,对所设计的移位寄存器进行抗单粒子翻转性能仿真验证.仿真结果表明,提出的双边复位POR和SEU加固DICE电路在LET为100 MeV·cm2/mg时不发生翻转.与传统的移位寄存器相比,设计的移位寄存器的抗单粒子翻转能力有显著的提高,具备高可靠性和辐射耐受性,可以用于航天领域的CMOS芯片设计.
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