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浙江大学学报(工学版)
JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE)  2017, Vol. 51 Issue (8): 1669-1675    DOI: 10.3785/j.issn.1008-973X.2017.08.025
Electrical and Electronic Engineering     
Low-dropout regulator with no off-chip capacitor and ultra low power consumption
CHEN Chen1, SUN Ke-xu2, FENG Jian-yu1, XI Jian-xiong1, HE Le-nian1
1. Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China;
2. Department of Electrical Engineering, Southern Methodist University Dallas, Texas, USA
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Abstract  

A LDO with an impedance-attenuated buffer was proposed to reduce power consumption and enhance stability with no off-chip capacitor. The LDO main loop adopted three-stage amplifier structure. Dynamically-biased shut feedback structure and slew rate enhancement circuit were used as an intermediate buffer for driving the pass device. The dominant pole was put on the output of the first-stage and the non-dominant poles were put on the output of the buffer and the output of the pass device by using the method of nested Miller compensation (NMC), realizing pole-pole tracking frequency compensation. The properties of stability and transient responses meet the design requirements. The proposed LDO was designed and implemented by using GSMC 130 nm CMOS process. The measured results showed that the output voltage was stable at 1.5 V when its input voltage was set to be changed from 1.6 to 4 V. The quiescent current was measured to be less than 881 nA at 1.5 mA output current. The designed circuit was validated by the results of the chip test.

Received: 01 August 2016      Published: 16 August 2017
CLC:  TN401  
  TN86  
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Cite this article:

CHEN Chen, SUN Ke-xu, FENG Jian-yu, XI Jian-xiong, HE Le-nian. Low-dropout regulator with no off-chip capacitor and ultra low power consumption. JOURNAL OF ZHEJIANG UNIVERSITY (ENGINEERING SCIENCE), 2017, 51(8): 1669-1675.

URL:

http://www.zjujournals.com/eng/10.3785/j.issn.1008-973X.2017.08.025     OR     http://www.zjujournals.com/eng/Y2017/V51/I8/1669


超低功耗无片外电容的低压差线性稳压器

为了减小无片外电容低压差线性稳压器（LDO）的功耗并提高稳定性，提出带有阻抗衰减缓冲器的LDO.该LDO主环路采用三级运放结构，具有动态偏置并联反馈结构和摆率增强电路的缓冲器作为中间级，驱动PMOS功率管.使用嵌套密勒补偿方式（NMC），将低频主极点放置在第一级输出，将缓冲器输出极点和LDO输出极点作为次极点构成极点-极点追踪，达到无片外电容LDO稳定性和瞬态响应的要求.芯片采用GSMC公司的130 nm CMOC工艺模型设计并经流片测试.测试结果表明：在1.6~4 V输入电压下，输出1.5 V电压，最大输出电流为1.5 mA时静态电流小于881 nA.测试结果验证了设计要求.

[1] QU X, ZHOU Z, ZHANG B, et al. An ultralow-power fast-transient capacitor-free low-dropout regulator with assistant push-pull output stage[J]. IEEE Transactions on Circuits and Systems Ⅱ:Express Briefs, 2013, 60(2):96-100.
[2] 王忆,何乐年.CMOS低压差线性稳压器[M].北京:科学出版社, 2012.
[3] LAM Y H, KI W H. A 0.9V 0.35μm adaptively biased CMOS LDO regulator with fast transient response[J]. IEEE, 2008, 51:442-626.
[4] LEE H, MOK P K T, LEUNG K N. Design of low-power analog drivers based on slew-rate enhancement circuits for CMOS low-dropout regulators[J]. Briefs IEEE Transactions on Circuits and Systems Ⅱ Express, 2005, 52(9):563-567.
[5] MAN T Y, MOK P K T, CHAN M. A high slew-rate push-pull output amplifier for low-quiescent current low-dropout regulators with transient-response improvement[J]. IEEE Transactions on Circuits and Systems Ⅱ Express Briefs, 2007, 54(9):755-759.
[6] ZHAN C, KI W H. An output-capacitor-free adaptively biased low-dropout regulator with sub-threshold undershoot-reduction for SoC[J]. IEEE Transactions on Circuits & Systems I Regular Papers, 2012, 59(5):45-48.
[7] OR P Y, LEUNG K N. An output-capacitorless low-dropout regulator with direct voltage-spike detection[J]. IEEE Journal of Solid-State Circuits, 2010, 45(2):458-466.
[8] GUO J P, LEUNG K N. A 6-μW Chip-area-efficient output-capacitorless LDO in 90-nm CMOS technology.[J]. IEEE Journal of Solid-State Circuits, 2010, 45(9):1896-1905.
[9] LEUNG K N, MOK P K T. Analysis of multistage amplifier-frequency compensation[J]. IEEE Transactions on Circuits and Systems I Fundamental Theory & Applications, 2001, 48(9):1041-1056.
[10] CUI C R, GONG W C, WANG Y, et al. Low dropout linear regulator with no off-chip capacitor and low power consumption[J]. Journal of Zhejiang University, 2009, 43(11):2006-2011.
[11] WANG Y, CUI C R. CMOS low-dropout regulator with 3.3μA quiescent current without off-chip capacitor[J]. Journal of Southeast University:English Edition, 2009, 25(2):441-445.
[12] ZHENG C, MA D. Notice of violation of IEEE publication principles design of monolithic low dropout regulator for wireless powered brain cortical implants using a line ripple rejection technique[J]. IEEE Transactions on Circuits & Systems Ⅱ Express Briefs, 2010, 57(9):686-690.
[13] KEIKHOSRAVY K, MIRABBASI S. A 0.13-μm CMOS low-power capacitor-less ldo regulator using bulk-modulation technique[J]. IEEE Transactions on Circuits & Systems I Regular Papers, 2014, 61(11):3105-3114.
[14] WANG J H, TSAI C H, LAI S W. A low-dropout regulator with tail current control for dpwm clock correction[J]. IEEE Transactions on Circuits and Systems Ⅱ Express Briefs, 2012, 59-Ⅱ(1):45-49.
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