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Searching the best polarity for fixed polarity Reed-Muller
circuits based on delay model |
| WANG Peng-jun1, WANG Zhen-hai1, CHEN Yao-wu2, LI Hui1 |
1. Institute of Circuits and Systems, Ningbo University, Ningbo 315211, China;
2. Institute of Advanced Digital Technologies and Instrumentation, Zhejiang University, Hangzhou 310027, China |
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Abstract To optimize delay of fixed polarity Reed-Muller (FPRM) circuits, a polarity searching algorithm was proposed for medium-scale ones to obtain the best polarity based on delay model. Within the frame of the proposed algorithm, FPRM expression of someone polarity was simplified by an algebraic method, the delay of corresponding estimated by Huffman-Like algorithm, and polarity conversion technique was used to search the best polarity exhaustively according to the characteristics of medium-scale integrated circuits. It was testified by 15 programmable logic array (PLA) formatted MCNC Benchmark circuits, and shows that it gains the average savage of 24.3% and 25% compared with two counterpart optimization algorithms on FPRM expression, and delay savage of 22.2% compared with optimization by sequential interactive system (SIS).
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Published: 01 February 2013
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固定极性Reed-Muller电路最佳延时极性搜索
为优化固定极性Reed-Muller（FPRM）电路延时,提出一种适合中小规模FPRM电路的最佳延时极性搜索算法.该算法利用代数法化简某一极性下的FPRM表达式,利用类Huffman算法估计该FPRM电路延时,根据中小规模集成电路的特点结合极性转换技术穷尽搜索延时最优的FPRM极性.对15个可编程逻辑阵列（PLA）格式MCNC Benchmark电路进行测试,结果表明：与其他2种FPRM表达式优化算法相比,与项数分别平均减少了24.3%和25%|与时序交互系统（SIS）优化后的电路相比,延时平均节省了22.2%.
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