基于三步旋转坐标旋转数字计算机算法的直接数字频率综合器实现

doi:10.3785/j.issn.1008-973X.2019.10.021

浙江大学学报(工学版)

2019, Vol. 53

Issue (10): 2034-2040 DOI: 10.3785/j.issn.1008-973X.2019.10.021

通信技术

基于三步旋转坐标旋转数字计算机算法的直接数字频率综合器实现

张亚云(

),刘家瑞*(

),王志宇,莫炯炯,郁发新

浙江大学航空航天学院，浙江杭州 310027

Implementation of direct digital frequency synthesizer based on three-step rotation coordinate rotation digital computer algorithm

Ya-yun ZHANG(

),Jia-rui LIU*(

),Zhi-yu WANG,Jiong-jiong MO,Fa-xin YU

College of Aeronautics and Astronautics, Zhejiang University, Hangzhou 310027, China

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摘要：

提出基于三步旋转机制的高精度低时延坐标旋转数字计算机 (CORDIC)算法. 该算法通过对输入角度进行二极化重编码来免除剩余旋转角度的运算，利用三步旋转机制对迭代次数进行压缩，结合合并迭代技术进一步减少迭代次数，降低输出时延. 以16位输出位宽为例，对三步旋转CORDIC算法和流水线迭代式算法进行实现，仿真结果表明：三步旋转CORDIC算法与流水线迭代式算法相比，改善了输出精度，输入到输出的时延降低了75%，硬件开销下降了29.2%. 基于三步旋转CORDIC算法，实现了相位累加器位宽为24的直接数字频率综合器 (DDFS)；使用加法树结构对多输入加法器进行优化，以提高电路工作频率. 仿真结果表明，该算法的最大幅度误差为8.24 × 10^?6，输出时延为38.5 ns.

关键词： 坐标旋转数字计算机 (CORDIC); 二极化重编码; 三步旋转; 合并迭代; 加法树; 现场可编程门阵列

Abstract:

A high precision and low output delay coordinate rotation digital computer (CORDIC) algorithm based on three-step rotation mechanism was proposed. The operation of the residual rotation angle was avoided by binary to bipolar recoding of the input angle, the number of iterations was compressed by three-step rotation mechanism, and the number of iterations and output delay were reduced by combining with merging iteration technique. The three-step rotation CORDIC algorithm and pipeline iterative algorithm were implemented by taking 16-bit output bit-width as an example. The simulation results show that the three-step rotation CORDIC algorithm improves the output accuracy, reduces the input-output delay by 75%, and reduces the hardware overhead by 29.2% compared with the pipeline iterative algorithm. The direct digital frequency synthesizer (DDFS) with a phase accumulator of 24 bits bit-width was implemented based on the three-step rotation CORDIC algorithm, and the multi-input adder was optimized with the addition tree structure in order to improve the circuit frequency. The simulation results showed that the maximum amplitude error of the algorithm was 8.24 × 10^?6, and the output delay was 38.5 ns.

Key words: coordinate rotation digital computer (CORDIC) binary to bipolar recoding three-step rotation merging iteration adder tree field programmable gate array

收稿日期: 2018-08-22 出版日期: 2019-09-30

CLC:

TN 431

通讯作者: 刘家瑞 E-mail: yyzhangstu@zju.edu.cn;jrliu@zju.edu.cn

作者简介: 张亚云(1994—)，女，硕士生，从事数字集成电路的研究. orcid.org/0000-0003-3640-689X. E-mail： yyzhangstu@zju.edu.cn

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引用本文:

张亚云,刘家瑞,王志宇,莫炯炯,郁发新. 基于三步旋转坐标旋转数字计算机算法的直接数字频率综合器实现[J]. 浙江大学学报(工学版), 2019, 53(10): 2034-2040.

Ya-yun ZHANG,Jia-rui LIU,Zhi-yu WANG,Jiong-jiong MO,Fa-xin YU. Implementation of direct digital frequency synthesizer based on three-step rotation coordinate rotation digital computer algorithm. Journal of ZheJiang University (Engineering Science), 2019, 53(10): 2034-2040.

链接本文:

http://www.zjujournals.com/eng/CN/10.3785/j.issn.1008-973X.2019.10.021 或 http://www.zjujournals.com/eng/CN/Y2019/V53/I10/2034

图 1 向量旋转图

图 2 三步旋转结构示意图

图 3 三步旋转算法实现框图

表 1 2种算法的性能对比

图 4 基于三步旋转的DDFS结构

图 5 3级加法树的示意图

图 6 Modelsim仿真图

图 7 三步旋转CORDIC算法的正、余弦值绝对误差

图 8 输出频率为120 MHz时的输出信号频谱图

表 2 4种方案的最大幅度误差、输出时延及硬件消耗对比

1	CHEN L B, HAN J, LIU W Q, et al Algorithm and design of a fully parallel approximate coordinate rotation digital computer (CORDIC)[J]. IEEE Transactions on Multi-Scale Computing Systems, 2017, 3 (3): 139- 151 doi: 10.1109/TMSCS.2017.2696003
2	AGGARWAL S, MEHER P K, KHARE K Concept, design, and implementation of reconfigurable CORDIC[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24 (4): 1588- 1592 doi: 10.1109/TVLSI.2015.2445855
3	MILFORD D, SANDELL M Singular value decomposition using an array of CORDIC processors[J]. Signal Processing, 2014, 102: 163- 170 doi: 10.1016/j.sigpro.2014.03.022
4	TANG A M, YU L, HAN F J, et al. CORDIC-based FFT real-time processing design and FPGA implementation [C]// 2016 IEEE 12th International Colloquium on Signal Processing and its Applications. Melaka, Malaysia: IEEE, 2016: 233-236.
5	SHABANI A, TIMARCHI S Low-power DCT-based compressor for wireless capsule endoscopy[J]. Signal Processing: Image Communication, 2017, 59: 83- 95 doi: 10.1016/j.image.2017.03.003
6	QU X J, CHEN H, ZHANG Y B, et al Design of DDS based on hybird-CORDIC architecture[J]. International Journal of Computational Intelligence Systems, 2011, 4 (3): 306- 313 doi: 10.1080/18756891.2011.9727787
7	ZHANG C Z, HAN J A, LI K Design and implementation of hybrid CORDIC algorithm based on phase rotation estimation for NCO[J]. The Scientific World Journal, 2014, 2014: 1- 8
8	KANG C Y, SWARTZLANDER E E. An analysis of the CORDIC algorithm for direct digital frequency synthesis [C]//IEEE International Conference on Application-Specific Systems, Architectures and Processors. San Jose, California: IEEE, 2002: 111-119.
9	VOLDER J E The CORDIC trigonometric computing technique[J]. IRE Transactions on Electronic Computers, 1959, EC-8 (3): 330- 334 doi: 10.1109/TEC.1959.5222693
10	史方显, 曾立, 陈昱, 等改进型高速高精度CORDIC算法及其在DDFS中的应用[J]. 电子学报, 2017, 45 (2): 446- 451 SHI Fang-xian, ZENG Li, CHEN Yu, et al Direct digital frequency synthesizer based on an improved high speed and high precision CORDIC algorithm[J]. Acta Electronica Sinica, 2017, 45 (2): 446- 451 doi: 10.3969/j.issn.0372-2112.2017.02.025
11	张佳, 唐威, 盛廷义, 等一种80位扩展双精度浮点三角函数运算单元的设计[J]. 微电子学与计算机, 2014, (4): 23- 26 ZHANG Jia, TANG Wei, SHENG Ting-yi, et al Design of a 80 bits extended double precision floating-point trigonometric computing unit[J]. Microelectronics and Computer, 2014, (4): 23- 26
12	徐成, 秦云川, 李肯立, 等免缩放因子双步旋转CORDIC算法[J]. 电子学报, 2014, 42 (7): 1441- 1445 XU Cheng, QIN Yun-chuan, LI Ken-li, et al Double-step scaling free CORDIC[J]. Acta Electronica Sinica, 2014, 42 (7): 1441- 1445 doi: 10.3969/j.issn.0372-2112.2014.07.031
13	祁艳杰, 刘章发基于Parallel_CORDIC的高精度高速度直接数字频率合成器的FPGA实现[J]. 电子学报, 2014, 42 (7): 1392- 1397 QI Yan-jie, LIU Zhang-fa FPGA implementation of high speed and high precision direct digital frequency synthesizer based on Parallel_CORDIC[J]. Acta Electronica Sinica, 2014, 42 (7): 1392- 1397 doi: 10.3969/j.issn.0372-2112.2014.07.023
14	MADISETTI A, KWENTUS A Y, WILLSON A N A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range[J]. IEEE Journal of Solid-State Circuits, 1999, 34 (8): 1034- 1043 doi: 10.1109/4.777100
15	姚亚峰, 付东兵, 杨晓非基于CORDIC改进算法的高速DDS电路设计[J]. 华中科技大学学报:自然科学版, 2009, (2): 25- 27 YAO Ya-feng, FU Dong-bing, YANG Xiao-fei Implement of high speed DDS circuit design using improved CORDIC algorithm[J]. Journal of Huazhong University of Science and Technology: Natural Science Edition, 2009, (2): 25- 27
16	JUANG T B, HSIAO S F, TSAI M Y Para-CORDIC: parallel CORDIC rotation algorithm[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2004, 51 (8): 1515- 1524 doi: 10.1109/TCSI.2004.832734
17	姚亚峰, 冯中秀, 陈朝超低时延免迭代 CORDIC 算法[J]. 西安电子科技大学学报, 2017, 44 (4): 162- 166 YAO Ya-feng, FENG Zhong-xiu, CHEN Zhao Ultra-low latency and omit-iteration CORDIC algorithm[J]. Journal of Xidian University, 2017, 44 (4): 162- 166 doi: 10.3969/j.issn.1001-2400.2017.04.028

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